MODELO SEMÂNTICO DE OPERAÇÕES ARITMÉTICAS E LÓGICAS PARA HARDWARE VIRTUAL

The objective of this project was to develop a semantic model of arithmetic and logical operations for virtual hardware; this goal was achieved through three main steps: Implement logic gates and arithmetic and logic units in Nand2tetris virtual hardware simulator software; Implement recursive and iterative functions to check the correct functioning of logical and arithmetic operations in the p-code machine virtual machine. In the first stage, implementations of the elementary logic gates were developed in the hardware simulator software Nand2tetris. From these logic gates, combinational circuits and sequential circuits were built as logical and arithmetic unit, Half Adder, Full Adder, 16-bit Addition, 16-bit logical negation, 16-bit logical AND, 16-bit logical OR, among others. The second stage involved experimenting at a high level with arithmetic and logical operations, provided by the virtual machine p-code machine, which was implemented in the C programming language, as addition, subtraction, greater than, less than. In the third stage, having already implemented logical and arithmetic operations, iterative and recursive programs were developed to calculate the nth value of the Fibonacci Sequence and the factorial of any number n.