Two-Stage Vernier-Based Time-to-Digital Converter with Enhanced Resolution and Digital Error Correction

This article proposes a two-stage time-to-digital converter with a novel method for enhancing resolution and using digital error correction called time-to-digital converter with enhanced resolution (TDC-ER). The proposed TDC is composed of two Vernier TDCs and operating in two stages. The first stage uses a normal Vernier TDC with a 512 ps range, and the second stage employs a 2D Vernier TDC with a new delay element. The second stage can achieve a fine resolution of 2 ps. This study presents a novel idea for boosting the resolution by analyzing D flip-flop (DFF) outputs in the metastability state. In the end, it is shown that this method can achieve a 1 ps resolution. The TDC-ER offers the benefits of new digital error correction, reducing the connection error between two stages and increasing linearity. A new calibration idea is presented in this work. This circuit is designed and simulated using a 65-nm standard CMOS technology, and the simulation result demonstrates a 1.56 ps effective resolution and a 9-bit range. It operates at 250 MS/s while consuming about 0.5 mW power from a 1.2-V supply.