Gangadharaiah Soralamavu Lakshmaiah, C. Narayanappa, Lakshmi Shrinivasan, Divya Muddenahalli Narasimhaiah
{"title":"比例型最小均方自适应滤波器的高效超大规模集成架构设计","authors":"Gangadharaiah Soralamavu Lakshmaiah, C. Narayanappa, Lakshmi Shrinivasan, Divya Muddenahalli Narasimhaiah","doi":"10.11591/ijres.v13.i1.pp69-75","DOIUrl":null,"url":null,"abstract":"The effectiveness of adaptive filters are mainly dependent on the design techniques and the algorithm of adaptation. The most common adaptation technique used is least mean square (LMS) due its computational simplicity. The application depends on the adaptive filter configuration used and are well known for system identification and real time applications. In this work, a modified delayed μ-law proportionate normalized least mean square (DMPNLMS) algorithm has been proposed. It is the improvised version of the µ-law proportionate normalized least mean square (MPNLMS) algorithm. The algorithm is realized using Ladner-Fischer type of parallel prefix logarithmic adder to reduce the silicon area. The simulation and implementation of very large-scale integration (VLSI) architecture are done using MATLAB, Vivado suite and complementary metal–oxide– semiconductor (CMOS) 90 nm technology node using Cadence register transfer level (RTL) Genus Compiler respectively. The DMPNLMS method exhibits a reduction in mean square error, a higher rate of convergence, and more stability. The synthesis results demonstrate that it is area and delay effective, making it practical for applications where a faster operating speed is required.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"76 22","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Efficient very large-scale integration architecture design of proportionate-type least mean square adaptive filters\",\"authors\":\"Gangadharaiah Soralamavu Lakshmaiah, C. Narayanappa, Lakshmi Shrinivasan, Divya Muddenahalli Narasimhaiah\",\"doi\":\"10.11591/ijres.v13.i1.pp69-75\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The effectiveness of adaptive filters are mainly dependent on the design techniques and the algorithm of adaptation. The most common adaptation technique used is least mean square (LMS) due its computational simplicity. The application depends on the adaptive filter configuration used and are well known for system identification and real time applications. In this work, a modified delayed μ-law proportionate normalized least mean square (DMPNLMS) algorithm has been proposed. It is the improvised version of the µ-law proportionate normalized least mean square (MPNLMS) algorithm. The algorithm is realized using Ladner-Fischer type of parallel prefix logarithmic adder to reduce the silicon area. The simulation and implementation of very large-scale integration (VLSI) architecture are done using MATLAB, Vivado suite and complementary metal–oxide– semiconductor (CMOS) 90 nm technology node using Cadence register transfer level (RTL) Genus Compiler respectively. The DMPNLMS method exhibits a reduction in mean square error, a higher rate of convergence, and more stability. The synthesis results demonstrate that it is area and delay effective, making it practical for applications where a faster operating speed is required.\",\"PeriodicalId\":158991,\"journal\":{\"name\":\"International Journal of Reconfigurable and Embedded Systems (IJRES)\",\"volume\":\"76 22\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Reconfigurable and Embedded Systems (IJRES)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.11591/ijres.v13.i1.pp69-75\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Reconfigurable and Embedded Systems (IJRES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.11591/ijres.v13.i1.pp69-75","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficient very large-scale integration architecture design of proportionate-type least mean square adaptive filters
The effectiveness of adaptive filters are mainly dependent on the design techniques and the algorithm of adaptation. The most common adaptation technique used is least mean square (LMS) due its computational simplicity. The application depends on the adaptive filter configuration used and are well known for system identification and real time applications. In this work, a modified delayed μ-law proportionate normalized least mean square (DMPNLMS) algorithm has been proposed. It is the improvised version of the µ-law proportionate normalized least mean square (MPNLMS) algorithm. The algorithm is realized using Ladner-Fischer type of parallel prefix logarithmic adder to reduce the silicon area. The simulation and implementation of very large-scale integration (VLSI) architecture are done using MATLAB, Vivado suite and complementary metal–oxide– semiconductor (CMOS) 90 nm technology node using Cadence register transfer level (RTL) Genus Compiler respectively. The DMPNLMS method exhibits a reduction in mean square error, a higher rate of convergence, and more stability. The synthesis results demonstrate that it is area and delay effective, making it practical for applications where a faster operating speed is required.