{"title":"优化 T 门和 CNOT 门的除法器和特殊乘法器设计","authors":"Ping Fan, Hai-Sheng Li","doi":"10.1140/epjqt/s40507-024-00222-4","DOIUrl":null,"url":null,"abstract":"<div><p>Quantum circuits for multiplication and division are necessary for scientific computing on quantum computers. Clifford + T circuits are widely used in fault-tolerant realizations. T gates are more expensive than other gates in Clifford + T circuits. But neglecting the cost of CNOT gates may lead to a significant underestimation. Moreover, the small number of qubits available in existing quantum devices is another constraint on quantum circuits. As a result, reducing T-count, T-depth, CNOT-count, CNOT-depth, and circuit width has become the important optimization goal. We use 3-bit Hermitian gates to design basic arithmetic operations. Then, we present a special multiplier and a divider using basic arithmetic operations, where ‘special’ means that one of the two operands of multiplication is non-zero. Next, we use new rules to optimize the Clifford + T circuits of the special multiplier and divider in terms of T-count, T-depth, CNOT-count, CNOT-depth, and circuit width. Comparative analysis shows that the proposed multiplier and divider have lower T-count, T-depth, CNOT-count, and CNOT-depth than the current works. For instance, the proposed 32-bit divider achieves improvement ratios of 40.41 percent, 31.64 percent, 45.27 percent, and 65.93 percent in terms of T-count, T-depth, CNOT-count, and CNOT-depth compared to the best current work. Further, the circuit widths of the proposed <i>n</i>-bit multiplier and divider are 3<i>n</i>. I.e., our multiplier and divider reach the minimum width of multipliers and dividers, keeping an operand unchanged.</p></div>","PeriodicalId":547,"journal":{"name":"EPJ Quantum Technology","volume":"11 1","pages":""},"PeriodicalIF":5.8000,"publicationDate":"2024-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://epjquantumtechnology.springeropen.com/counter/pdf/10.1140/epjqt/s40507-024-00222-4","citationCount":"0","resultStr":"{\"title\":\"Designs of the divider and special multiplier optimizing T and CNOT gates\",\"authors\":\"Ping Fan, Hai-Sheng Li\",\"doi\":\"10.1140/epjqt/s40507-024-00222-4\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>Quantum circuits for multiplication and division are necessary for scientific computing on quantum computers. Clifford + T circuits are widely used in fault-tolerant realizations. T gates are more expensive than other gates in Clifford + T circuits. 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引用次数: 0
摘要
在量子计算机上进行科学计算需要乘除量子电路。克利福德 + T 电路广泛用于容错实现。在 Clifford + T 电路中,T 门比其他门更昂贵。但忽略 CNOT 门的成本可能会导致严重低估。此外,现有量子设备的量子比特数量较少,这也是量子电路的另一个限制因素。因此,减少 T 数、T 深度、CNOT 数、CNOT 深度和电路宽度成为重要的优化目标。我们使用 3 位 Hermitian 门来设计基本算术运算。然后,我们利用基本算术运算提出了一个特殊的乘法器和一个除法器,其中 "特殊 "是指乘法的两个操作数之一为非零。接下来,我们使用新规则,从 T 数、T 深度、CNOT 数、CNOT 深度和电路宽度等方面优化了特殊乘法器和除法器的 Clifford + T 电路。对比分析表明,与现有的乘法器和除法器相比,建议的乘法器和除法器具有更低的 T-count、T-depth、CNOT-count 和 CNOT-depth。例如,与目前最好的作品相比,拟议的 32 位除法器在 T-count、T-depth、CNOT-count 和 CNOT-depth 方面分别实现了 40.41%、31.64%、45.27% 和 65.93% 的改进率。此外,建议的 n 位乘法器和除法器的电路宽度为 3n。也就是说,在操作数不变的情况下,我们的乘法器和除法器达到了乘法器和除法器的最小宽度。
Designs of the divider and special multiplier optimizing T and CNOT gates
Quantum circuits for multiplication and division are necessary for scientific computing on quantum computers. Clifford + T circuits are widely used in fault-tolerant realizations. T gates are more expensive than other gates in Clifford + T circuits. But neglecting the cost of CNOT gates may lead to a significant underestimation. Moreover, the small number of qubits available in existing quantum devices is another constraint on quantum circuits. As a result, reducing T-count, T-depth, CNOT-count, CNOT-depth, and circuit width has become the important optimization goal. We use 3-bit Hermitian gates to design basic arithmetic operations. Then, we present a special multiplier and a divider using basic arithmetic operations, where ‘special’ means that one of the two operands of multiplication is non-zero. Next, we use new rules to optimize the Clifford + T circuits of the special multiplier and divider in terms of T-count, T-depth, CNOT-count, CNOT-depth, and circuit width. Comparative analysis shows that the proposed multiplier and divider have lower T-count, T-depth, CNOT-count, and CNOT-depth than the current works. For instance, the proposed 32-bit divider achieves improvement ratios of 40.41 percent, 31.64 percent, 45.27 percent, and 65.93 percent in terms of T-count, T-depth, CNOT-count, and CNOT-depth compared to the best current work. Further, the circuit widths of the proposed n-bit multiplier and divider are 3n. I.e., our multiplier and divider reach the minimum width of multipliers and dividers, keeping an operand unchanged.
期刊介绍:
Driven by advances in technology and experimental capability, the last decade has seen the emergence of quantum technology: a new praxis for controlling the quantum world. It is now possible to engineer complex, multi-component systems that merge the once distinct fields of quantum optics and condensed matter physics.
EPJ Quantum Technology covers theoretical and experimental advances in subjects including but not limited to the following:
Quantum measurement, metrology and lithography
Quantum complex systems, networks and cellular automata
Quantum electromechanical systems
Quantum optomechanical systems
Quantum machines, engineering and nanorobotics
Quantum control theory
Quantum information, communication and computation
Quantum thermodynamics
Quantum metamaterials
The effect of Casimir forces on micro- and nano-electromechanical systems
Quantum biology
Quantum sensing
Hybrid quantum systems
Quantum simulations.