可积分仿真浮动递增/递减反向忆阻器以扩展忆阻器带宽

K. Bhardwaj, Ravuri Narayana, Dheeraj Kalra, Mayank Srivastava
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引用次数: 0

摘要

文章通过基于电路的方法,探讨了反向忆阻器的紧凑型仿真。文章介绍了一种浮动仿真器架构,它结合了双输出 OTA(操作跨导放大器)和 DVCC(差分电压电流传输器)以及两个接地无源元件,以实现反向忆阻器的仿真。利用接地电阻可对实现的行为进行调整。这项研究的一个重要贡献是将反向忆阻器用于扩展任何忆阻器仿真器电路的工作频率范围。在 0.18 µm TSMC CMOS 技术中,利用 PSPICE 生成的仿真结果,在增量和减量模式下对所提出的仿真器电路及其应用进行了验证。此外,还介绍了采用集成电路 LM13700 的反向忆阻器仿真器配置,并通过面包板实现对其功能进行了测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Integrable emulation of a floating incremental/decremental inverse memristor for memristor bandwidth extension
The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation.
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