LL-GNN:高能物理 FPGA 上的低延迟图神经网络

IF 2.8 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Zhiqiang Que, Hongxiang Fan, Marcus Loo, He Li, Michaela Blott, Maurizio Pierini, Alexander Tapper, Wayne Luk
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引用次数: 0

摘要

这项研究为粒子探测器的低延迟图神经网络(LL-GNN)设计提出了一种新颖的可重新配置架构,可提供前所未有的低延迟性能。将基于 FPGA 的 GNN 纳入粒子探测器是一项独特的挑战,因为在欧洲核子研究中心(CERN)大型强子对撞机实验的一级触发器中,需要亚微秒级的延迟来部署网络,以每秒数百 TB 的数据速率进行在线事件选择。本文提出了一种新颖的基于外积的矩阵乘法方法,该方法通过利用结构化邻接矩阵和列主数据布局得到了增强。此外,我们还为矩阵乘法运算提出了一种定制代码转换,利用邻接矩阵的结构稀疏性模式和二进制特征来减少延迟并提高硬件效率。此外,还引入了融合步骤,通过消除不必要的边界来进一步减少端到端设计延迟。此外,还提出了一种针对 GNN 的算法-硬件协同设计方法,该方法不仅能找到延迟更短的设计,还能在给定的延迟限制条件下找到高精度设计。为此,我们为这种低延迟 GNN 硬件架构设计了一个可定制的模板,并将其开源,从而能够使用高级综合工具生成资源利用率高的低延迟 FPGA 设计。评估结果表明,我们的 FPGA 实现比 GPU 实现快达 9.0 倍,功耗效率高达 13.1 倍。与之前的 FPGA 实现相比,这项工作实现了 6.51 到 16.7 倍的低延迟。此外,我们的 FPGA 设计的延迟足够低,可以在亚微秒级实时对撞机触发系统中部署 GNN,使其受益于更高的精度。所提出的 LL-GNN 设计使复杂的算法能够高效地处理实验数据,从而推动了下一代触发系统的发展。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics

This work presents a novel reconfigurable architecture for Low Latency Graph Neural Network (LL-GNN) designs for particle detectors, delivering unprecedented low latency performance. Incorporating FPGA-based GNNs into particle detectors presents a unique challenge since it requires sub-microsecond latency to deploy the networks for online event selection with a data rate of hundreds of terabytes per second in the Level-1 triggers at the CERN Large Hadron Collider experiments. This paper proposes a novel outer-product based matrix multiplication approach, which is enhanced by exploiting the structured adjacency matrix and a column-major data layout. In addition, we propose a custom code transformation for the matrix multiplication operations, which leverages the structured sparsity patterns and binary features of adjacency matrices to reduce latency and improve hardware efficiency. Moreover, a fusion step is introduced to further reduce the end-to-end design latency by eliminating unnecessary boundaries. Furthermore, a GNN-specific algorithm-hardware co-design approach is presented which not only finds a design with a much better latency but also finds a high accuracy design under given latency constraints. To facilitate this, a customizable template for this low latency GNN hardware architecture has been designed and open-sourced, which enables the generation of low-latency FPGA designs with efficient resource utilization using a high-level synthesis tool. Evaluation results show that our FPGA implementation is up to 9.0 times faster and achieves up to 13.1 times higher power efficiency than a GPU implementation. Compared to the previous FPGA implementations, this work achieves 6.51 to 16.7 times lower latency. Moreover, the latency of our FPGA design is sufficiently low to enable deployment of GNNs in a sub-microsecond, real-time collider trigger system, enabling it to benefit from improved accuracy. The proposed LL-GNN design advances the next generation of trigger systems by enabling sophisticated algorithms to process experimental data efficiently.

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来源期刊
ACM Transactions on Embedded Computing Systems
ACM Transactions on Embedded Computing Systems 工程技术-计算机:软件工程
CiteScore
3.70
自引率
0.00%
发文量
138
审稿时长
6 months
期刊介绍: The design of embedded computing systems, both the software and hardware, increasingly relies on sophisticated algorithms, analytical models, and methodologies. ACM Transactions on Embedded Computing Systems (TECS) aims to present the leading work relating to the analysis, design, behavior, and experience with embedded computing systems.
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