Jing Tian, Zhipeng Sun, Songbo Chang, Yi Qian, Hongyun Zhao, Zhengguo Hu
{"title":"HSPC - 用于 HFRS-TPC 的高速 PCIe 读卡器","authors":"Jing Tian, Zhipeng Sun, Songbo Chang, Yi Qian, Hongyun Zhao, Zhengguo Hu","doi":"10.1088/1748-0221/18/12/P12008","DOIUrl":null,"url":null,"abstract":"A new High-Speed PCI Express (PCIe) readout Card (HSPC) has been designed to transmit and aggregate data from the Time Projection Chamber (TPC) that will be assembled on High energy FRagment Separator (HFRS) beamlines at the High Intensity heavy-ion Accelerator Facility (HIAF) currently being built in Huizhou City, China. The HSPC features a high-performance controller utilizing the Xilinx Kintex Ultrascale Series Field Programmable Gate Array (FPGA), two Quad Small Form-factor Pluggable Plus (QSFP+) connectors, and a PCIe Gen3×8 interface with theoretical bandwidth of 64 Gbps. Experimental testing shows that there are no errors on the 8-fiber optics when operating at 9.6 Gbps per link, and the bit error rate (BER) is less than 1.0 × 10-15. In addition, the total read bandwidth of PCIe Gen3×8 reaches 7085.4 MB/s. Consequently, the HSPC can meet HFRS requirements.","PeriodicalId":16184,"journal":{"name":"Journal of Instrumentation","volume":"194 ","pages":""},"PeriodicalIF":1.3000,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The HSPC — a high speed PCIe readout card for the HFRS-TPC\",\"authors\":\"Jing Tian, Zhipeng Sun, Songbo Chang, Yi Qian, Hongyun Zhao, Zhengguo Hu\",\"doi\":\"10.1088/1748-0221/18/12/P12008\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new High-Speed PCI Express (PCIe) readout Card (HSPC) has been designed to transmit and aggregate data from the Time Projection Chamber (TPC) that will be assembled on High energy FRagment Separator (HFRS) beamlines at the High Intensity heavy-ion Accelerator Facility (HIAF) currently being built in Huizhou City, China. The HSPC features a high-performance controller utilizing the Xilinx Kintex Ultrascale Series Field Programmable Gate Array (FPGA), two Quad Small Form-factor Pluggable Plus (QSFP+) connectors, and a PCIe Gen3×8 interface with theoretical bandwidth of 64 Gbps. Experimental testing shows that there are no errors on the 8-fiber optics when operating at 9.6 Gbps per link, and the bit error rate (BER) is less than 1.0 × 10-15. In addition, the total read bandwidth of PCIe Gen3×8 reaches 7085.4 MB/s. Consequently, the HSPC can meet HFRS requirements.\",\"PeriodicalId\":16184,\"journal\":{\"name\":\"Journal of Instrumentation\",\"volume\":\"194 \",\"pages\":\"\"},\"PeriodicalIF\":1.3000,\"publicationDate\":\"2023-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Instrumentation\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1088/1748-0221/18/12/P12008\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"INSTRUMENTS & INSTRUMENTATION\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Instrumentation","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1088/1748-0221/18/12/P12008","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"INSTRUMENTS & INSTRUMENTATION","Score":null,"Total":0}
The HSPC — a high speed PCIe readout card for the HFRS-TPC
A new High-Speed PCI Express (PCIe) readout Card (HSPC) has been designed to transmit and aggregate data from the Time Projection Chamber (TPC) that will be assembled on High energy FRagment Separator (HFRS) beamlines at the High Intensity heavy-ion Accelerator Facility (HIAF) currently being built in Huizhou City, China. The HSPC features a high-performance controller utilizing the Xilinx Kintex Ultrascale Series Field Programmable Gate Array (FPGA), two Quad Small Form-factor Pluggable Plus (QSFP+) connectors, and a PCIe Gen3×8 interface with theoretical bandwidth of 64 Gbps. Experimental testing shows that there are no errors on the 8-fiber optics when operating at 9.6 Gbps per link, and the bit error rate (BER) is less than 1.0 × 10-15. In addition, the total read bandwidth of PCIe Gen3×8 reaches 7085.4 MB/s. Consequently, the HSPC can meet HFRS requirements.
期刊介绍:
Journal of Instrumentation (JINST) covers major areas related to concepts and instrumentation in detector physics, accelerator science and associated experimental methods and techniques, theory, modelling and simulations. The main subject areas include.
-Accelerators: concepts, modelling, simulations and sources-
Instrumentation and hardware for accelerators: particles, synchrotron radiation, neutrons-
Detector physics: concepts, processes, methods, modelling and simulations-
Detectors, apparatus and methods for particle, astroparticle, nuclear, atomic, and molecular physics-
Instrumentation and methods for plasma research-
Methods and apparatus for astronomy and astrophysics-
Detectors, methods and apparatus for biomedical applications, life sciences and material research-
Instrumentation and techniques for medical imaging, diagnostics and therapy-
Instrumentation and techniques for dosimetry, monitoring and radiation damage-
Detectors, instrumentation and methods for non-destructive tests (NDT)-
Detector readout concepts, electronics and data acquisition methods-
Algorithms, software and data reduction methods-
Materials and associated technologies, etc.-
Engineering and technical issues.
JINST also includes a section dedicated to technical reports and instrumentation theses.