后量子特征晶体-锂的高性能可配置SW/HW协同设计

IF 3.1 4区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Gaoyu Mao, Donglong Chen, Guangyan Li, Wangchen Dai, Abdurrashid Ibrahim Sanka, Çetin Kaya Koç, Ray C. C. Cheung
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引用次数: 0

摘要

CRYSTALS-Dilithium是一种基于晶格的后量子数字签名方案,可抵抗量子计算机的攻击,并已被选中在NIST后量子密码学(PQC)标准化过程中进行标准化。但其速度性能和设计灵活性仍有待进一步评估。本文提出了一种基于NIST PQC round-3参数的晶体-二锂高性能软硬件协同设计方法。设计中包含用于NTT/INTT,点乘法/加法和SHAKE的高速流水线硬件模块,以加速耗时的Dilithium操作。所有硬件模块都是参数化的,因此允许完全支持运行时配置以增加多功能性。此外,所提出的软/硬件架构和紧凑的操作工作流减少了处理器与其他硬件模块之间的数据传输开销。硬件加速器在FPGA上采用可重构逻辑实现,并与Xilinx Zynq架构中的高性能ARM Cortex-A9处理器集成。我们在NIST安全级别2、3和5中测量了Dilithium软件/硬件系统的性能。与纯软件实现相比,我们在密钥生成方面实现了8.7-12.5倍的加速,在签名方面实现了6.3-7.3倍的加速,在验证操作方面实现了9.1-12.2倍的加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium

CRYSTALS-Dilithium is a lattice-based post-quantum digital signature scheme that is resistant to attacks by quantum computers and has been selected to be standardized in the NIST post-quantum cryptography (PQC) standardization process. However, the speed performance and design flexibility of the Dilithium still need to be evaluated. This article presents a high-performance software/hardware co-design of CRYSTALS-Dilithium based on the NIST PQC round-3 parameters. High-speed pipelined hardware modules for NTT/INTT, point-wise multiplication/addition, and for SHAKE are included in the design to accelerate the time-consuming operations in Dilithium. All hardware modules are parameterized, thus allowing full support of runtime configuration to increase versatility. Moreover, the proposed software/hardware architecture and tight operating workflows reduce the data transmission overhead between the processor and other hardware modules. The hardware accelerator is implemented with a reconfigurable logic on FPGA and is integrated with the high-performance ARM Cortex-A9 processor in the Xilinx Zynq Architecture. We measure the performance of the software/hardware system for Dilithium in NIST security levels 2, 3, and 5. Compared to pure software implementations, we achieve 8.7–12.5 times speedup in Key generation, 6.3–7.3 times speedup in Sign, and 9.1–12.2 times speedup in Verify operations.

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来源期刊
ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.90
自引率
8.70%
发文量
79
审稿时长
>12 weeks
期刊介绍: TRETS is the top journal focusing on research in, on, and with reconfigurable systems and on their underlying technology. The scope, rationale, and coverage by other journals are often limited to particular aspects of reconfigurable technology or reconfigurable systems. TRETS is a journal that covers reconfigurability in its own right. Topics that would be appropriate for TRETS would include all levels of reconfigurable system abstractions and all aspects of reconfigurable technology including platforms, programming environments and application successes that support these systems for computing or other applications. -The board and systems architectures of a reconfigurable platform. -Programming environments of reconfigurable systems, especially those designed for use with reconfigurable systems that will lead to increased programmer productivity. -Languages and compilers for reconfigurable systems. -Logic synthesis and related tools, as they relate to reconfigurable systems. -Applications on which success can be demonstrated. The underlying technology from which reconfigurable systems are developed. (Currently this technology is that of FPGAs, but research on the nature and use of follow-on technologies is appropriate for TRETS.) In considering whether a paper is suitable for TRETS, the foremost question should be whether reconfigurability has been essential to success. Topics such as architecture, programming languages, compilers, and environments, logic synthesis, and high performance applications are all suitable if the context is appropriate. For example, an architecture for an embedded application that happens to use FPGAs is not necessarily suitable for TRETS, but an architecture using FPGAs for which the reconfigurability of the FPGAs is an inherent part of the specifications (perhaps due to a need for re-use on multiple applications) would be appropriate for TRETS.
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