模拟内存计算神经网络加速器的极值部分和量化

IF 2.1 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim
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引用次数: 0

摘要

在内存模拟计算(CIM)神经网络加速器中,需要模数转换器(adc)将CIM阵列生成的模拟部分和转换为数字值。ADC的开销大大降低了CIM加速器的能源效率,因此以前的工作试图降低ADC的分辨率,考虑到部分和的分布。尽管如此,所需的ADC分辨率仍然相对较高。在本文中,我们提出了数据驱动的部分和量化方案,该方案在计算量很小的情况下穷尽搜索最优量化范围。我们还报告说,与之前主要使用整个网络的部分和分布特征的工作相比,分析每层部分和分布的特征提供了额外的信息,以进一步降低ADC分辨率。基于精细级数据驱动方法和再训练相结合,提出了一种极值部分和量化方法。实验结果表明,该方法可以将CIFAR-10数据集的ADC分辨率降低到2 ~ 3位,比以往任何基于cim的神经网络加速器的ADC位分辨率都要小。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators

In Analog Computing-in-Memory (CIM) neural network accelerators, analog-to-digital converters (ADCs) are required to convert the analog partial sums generated from a CIM array to digital values. The overhead from ADCs substantially degrades the energy efficiency of CIM accelerators so that previous works attempted to lower the ADC resolution considering the distribution of the partial sums. Despite the efforts, the required ADC resolution still remains relatively high. In this article, we propose the data-driven partial sum quantization scheme, which exhaustively searches for the optimal quantization range with little computational burden. We also report that analyzing the characteristics of the partial sum distributions at each layer gives an additional information to further reduce the ADC resolution compared to previous works that mostly used the characteristics of the partial sum distributions of the entire network. Based on the finer-level data-driven approach combined with retraining, we present a methodology for extreme partial-sum quantization. Experimental results show that the proposed method can reduce the ADC resolution to 2 to 3 bits for CIFAR-10 dataset, which is the smaller ADC bit resolution than any previous CIM-based NN accelerators.

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来源期刊
ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems 工程技术-工程:电子与电气
CiteScore
4.80
自引率
4.50%
发文量
86
审稿时长
3 months
期刊介绍: The Journal of Emerging Technologies in Computing Systems invites submissions of original technical papers describing research and development in emerging technologies in computing systems. Major economic and technical challenges are expected to impede the continued scaling of semiconductor devices. This has resulted in the search for alternate mechanical, biological/biochemical, nanoscale electronic, asynchronous and quantum computing and sensor technologies. As the underlying nanotechnologies continue to evolve in the labs of chemists, physicists, and biologists, it has become imperative for computer scientists and engineers to translate the potential of the basic building blocks (analogous to the transistor) emerging from these labs into information systems. Their design will face multiple challenges ranging from the inherent (un)reliability due to the self-assembly nature of the fabrication processes for nanotechnologies, from the complexity due to the sheer volume of nanodevices that will have to be integrated for complex functionality, and from the need to integrate these new nanotechnologies with silicon devices in the same system. The journal provides comprehensive coverage of innovative work in the specification, design analysis, simulation, verification, testing, and evaluation of computing systems constructed out of emerging technologies and advanced semiconductors
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