使用ReRAM用于神经网络加速器的可编程非线性电路

IF 3.1 4区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Rafael Fão de Moura, Luigi Carro
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引用次数: 0

摘要

随着人工智能(AI)技术在经济中的广泛应用,研究人员正在探索新的技术来降低神经网络(NN)应用的能耗,特别是随着神经网络复杂性的不断增加。使用模拟电阻性RAM (ReRAM)设备以0(1)时间复杂度计算矩阵向量乘法(MVM)是一种很有前途的方法,但这些实现通常无法覆盖现代神经网络应用所需的非线性多样性。在这项工作中,我们提出了一种新的方法,其中reram本身可以重新编程,不仅可以计算所需的矩阵乘法,还可以计算激活函数,softmax和池化层,从而减少复杂神经网络中的能量。与自定义逻辑相比,这种方法为研究新颖的神经网络布局提供了更多的通用性。结果表明,在使用卷积神经网络(cnn)、生成式预训练变压器(GPT)和长短期记忆(LSTM)模型的现实世界人类活动识别和语言建模数据集的实验中,我们的设备比模拟和数字现场可编程方法高出8.5倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Reprogrammable non-linear circuits using ReRAM for NN accelerators
As the massive usage of Artificial Intelligence (AI) techniques spreads in the economy, researchers are exploring new techniques to reduce the energy consumption of Neural Network (NN) applications, especially as the complexity of NNs continues to increase. Using analog Resistive RAM (ReRAM) devices to compute Matrix-Vector Multiplication (MVM) in O (1) time complexity is a promising approach, but it’s true that these implementations often fail to cover the diversity of nonlinearities required for modern NN applications. In this work, we propose a novel approach where ReRAMs themselves can be reprogrammed to compute not only the required matrix multiplications, but also the activation functions, softmax, and pooling layers, reducing energy in complex NNs. This approach offers more versatility for researching novel NN layouts compared to custom logic. Results show that our device outperforms analog and digital Field Programmable approaches by up to 8.5x in experiments on real-world human activity recognition and language modeling datasets with Convolutional Neural Networks (CNNs), Generative Pre-trained Transformer (GPT), and Long Short-Term Memory (LSTM) models.
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来源期刊
ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.90
自引率
8.70%
发文量
79
审稿时长
>12 weeks
期刊介绍: TRETS is the top journal focusing on research in, on, and with reconfigurable systems and on their underlying technology. The scope, rationale, and coverage by other journals are often limited to particular aspects of reconfigurable technology or reconfigurable systems. TRETS is a journal that covers reconfigurability in its own right. Topics that would be appropriate for TRETS would include all levels of reconfigurable system abstractions and all aspects of reconfigurable technology including platforms, programming environments and application successes that support these systems for computing or other applications. -The board and systems architectures of a reconfigurable platform. -Programming environments of reconfigurable systems, especially those designed for use with reconfigurable systems that will lead to increased programmer productivity. -Languages and compilers for reconfigurable systems. -Logic synthesis and related tools, as they relate to reconfigurable systems. -Applications on which success can be demonstrated. The underlying technology from which reconfigurable systems are developed. (Currently this technology is that of FPGAs, but research on the nature and use of follow-on technologies is appropriate for TRETS.) In considering whether a paper is suitable for TRETS, the foremost question should be whether reconfigurability has been essential to success. Topics such as architecture, programming languages, compilers, and environments, logic synthesis, and high performance applications are all suitable if the context is appropriate. For example, an architecture for an embedded application that happens to use FPGAs is not necessarily suitable for TRETS, but an architecture using FPGAs for which the reconfigurability of the FPGAs is an inherent part of the specifications (perhaps due to a need for re-use on multiple applications) would be appropriate for TRETS.
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