Improved Stability for Robust and Low-Power SRAM Cell using FinFET Technology

In the current nanoscale regime, fin field effect transistor (FinFET) technology overcomes the limitations of metal oxide semiconductor field effect transistor (MOSFET) technology. Robust and low-power static random access memory (SRAM) design is a demanding task for memory designers, especially in the nanoscale regime. Therefore, this paper proposes a 10 transistor (10T)-based SRAM cell design using low-power FinFET technology. The proposed approach not only reduces the leakage current, but also improves cell stability in different states. The proposed SRAM cell is simulated and analyzed at a 10[Formula: see text]nm technology node using a multi-gate predictive technology model (PTM) for the transistors with a power supply of 0.7[Formula: see text]V. The comparison analysis is also presented with the existing designs. The read and write static noise margins, and SRAM electrical quantity matrix (SEQM) of the proposed SRAM cell are improved by 3.54×, 1.71× and 26.41×, respectively, compared with the conventional 6T (C6T) design. The reliability investigations and comparison of the proposed SRAM cell have been carried out using Monte Carlo simulations with [Formula: see text]% deviations in the process parameters. The reliability analysis shows that the proposed SRAM cell is less sensitive to process variations.