利用SG翅片FET设计高效低功耗静态逻辑电路

IF 1.1 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Venkatesan RameyaSridharan, Manjunathan Alagarsamy, Balamurugan Rajangam, Lalitha Sekar
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引用次数: 0

摘要

摘要集成密度的提高和电池供电器件效率的提高降低了互补金属氧化物半导体(CMOS)技术的节点。在CMOS技术中,对元件的影响主要有漏功率、动态开关功率、短路功率、栅氧化物隧道漏电流、亚阈值漏电流等。为了减少上述限制,本文提出了采用基于输入依赖(INDEP)的22 nm CMOS技术(SLC-SG-FinFET- INDEP-22 nm CMOS)的短栅(SG)鳍场效应晶体管(FinFET)设计高效低功耗静态逻辑电路。提出的INDEP finfet模型采用更好的输入选择来降低泄漏功率。采用延迟、功率、功率延迟积分析了SLC-SG-FinFET- indep - 22nm CMOS技术的效率,并采用噪声裕度分析了稳定性。因此,与现有的22 nm CMOS (SLC-ICLRT-22 nm CMOS)静态逻辑电路输入控制的泄漏抑制晶体管相比,所提出的SLC-SG-FinFET-INDEP-22 nm CMOS延迟降低21.31%、41.47%和12.7%,功耗降低20.87%、34.5%和22.41%,速度提高4.5%、25.7%和32.11%。采用自控制漏抑制块的22 nm CMOS静态逻辑电路(SLC-SCLSB-22 nm CMOS)和采用计算数字低差的22 nm CMOS静态逻辑电路(SLC-CDLDO-22 nm CMOS)方法。关键词:互补金属氧化物半导体(CMOS)漏功耗22nm CMOS技术静态逻辑门输入依赖(INDEP) finfetet免责声明作为对作者和研究人员的服务,我们提供此版本的接受稿件(AM)。在最终出版版本记录(VoR)之前,将对该手稿进行编辑、排版和审查。在制作和印前,可能会发现可能影响内容的错误,所有适用于期刊的法律免责声明也与这些版本有关。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of high efficient low power static logic circuit using SG fin FET
ABSTRACTThe increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor ;(CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, Gate Oxide Tunneling Leakage Current, Sub threshold Leakage Current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS Technology(SLC-SG-FinFET- INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET- INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using Noise Margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS Technology (SLC-SCLSB-22 nm CMOS),and static logic circuit using computational digital low dropout in 22 nm CMOS Technology(SLC-CDLDO-22 nm CMOS) methods respectively.KEYWORDS: Complementary metal-oxide semiconductor (CMOS)leakage power dissipation22nm CMOS technologystatic logic gatesInput dependent (INDEP) FinFETDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
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来源期刊
International Journal of Electronics
International Journal of Electronics 工程技术-工程:电子与电气
CiteScore
3.30
自引率
15.40%
发文量
110
审稿时长
8 months
期刊介绍: The International Journal of Electronics (IJE) supports technical applications and developing research at the cutting edge of electronics. Encompassing a broad range of electronic topics, we are a leading electronics journal dedicated to quickly sharing new concepts and developments the field of electronics.
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