基于决策树的多目标强化学习在特定领域片上系统中的运行时任务调度

IF 2.8 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Toygun Basaklar, A. Alper Goksoy, Anish Krishnakumar, Suat Gumussoy, Umit Y. Ogras
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引用次数: 0

摘要

特定领域的片上系统(dssoc)结合了通用处理器和专用硬件加速器,以提高特定领域的性能和能源效率。以最小的运行时开销将任务优化分配给处理元素(pe)对于实现这一潜力至关重要。然而,这个问题仍然具有挑战性,因为先前的方法受到非最佳调度决策或显著运行时开销的影响。此外,现有的技术只关注于单一的优化目标,例如最大化性能。这项工作提出了DTRL,一种基于决策树的多目标强化学习技术,用于dssoc的运行时任务调度。DTRL训练一个全局可微决策树(DDT)策略,该策略覆盖由偏好向量量化的整个目标空间。我们使用我们的新型强化学习环境进行了广泛的实验评估,证明DTRL捕获了执行时间和功耗之间的权衡,从而使用单个策略生成了Pareto解决方案集。此外,与最先进的启发式、优化和基于机器学习的调度器进行比较表明,DTRL实现了高达9倍的性能提升和高达3.08倍的能耗降低。训练后的DDT策略在Xilinx Zynq ZCU102 FPGA上实现了1.2 GHz的120 ns推理延迟,导致运行时开销可以忽略不计。对相同硬件的评估表明,DTRL的性能比最先进的启发式调度器高出16%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
DTRL: Decision Tree-based Multi-Objective Reinforcement Learning for Runtime Task Scheduling in Domain-Specific System-on-Chips
Domain-specific systems-on-chip (DSSoCs) combine general-purpose processors and specialized hardware accelerators to improve performance and energy efficiency for a specific domain. The optimal allocation of tasks to processing elements (PEs) with minimal runtime overheads is crucial to achieving this potential. However, this problem remains challenging as prior approaches suffer from non-optimal scheduling decisions or significant runtime overheads. Moreover, existing techniques focus on a single optimization objective, such as maximizing performance. This work proposes DTRL, a decision-tree-based multi-objective reinforcement learning technique for runtime task scheduling in DSSoCs. DTRL trains a single global differentiable decision tree (DDT) policy that covers the entire objective space quantified by a preference vector. Our extensive experimental evaluations using our novel reinforcement learning environment demonstrate that DTRL captures the trade-off between execution time and power consumption, thereby generating a Pareto set of solutions using a single policy. Furthermore, comparison with state-of-the-art heuristic–, optimization–, and machine learning-based schedulers shows that DTRL achieves up to 9× higher performance and up to 3.08× reduction in energy consumption. The trained DDT policy achieves 120 ns inference latency on Xilinx Zynq ZCU102 FPGA at 1.2 GHz, resulting in negligible runtime overheads. Evaluation on the same hardware shows that DTRL achieves up to 16% higher performance than a state-of-the-art heuristic scheduler.
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来源期刊
ACM Transactions on Embedded Computing Systems
ACM Transactions on Embedded Computing Systems 工程技术-计算机:软件工程
CiteScore
3.70
自引率
0.00%
发文量
138
审稿时长
6 months
期刊介绍: The design of embedded computing systems, both the software and hardware, increasingly relies on sophisticated algorithms, analytical models, and methodologies. ACM Transactions on Embedded Computing Systems (TECS) aims to present the leading work relating to the analysis, design, behavior, and experience with embedded computing systems.
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