基于故障注入机制的网络安全攻击可靠性评估仿真方法

IF 0.9 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Shaminder Kaur, Ashish Sachdeva
{"title":"基于故障注入机制的网络安全攻击可靠性评估仿真方法","authors":"Shaminder Kaur, Ashish Sachdeva","doi":"10.1142/s021812662450097x","DOIUrl":null,"url":null,"abstract":"Clock attacks and power attacks are used as common means to inject faults in embedded devices. Critical analysis of the properties and the components engaged with these fault injection methods is of high importance to assess the related dangers and furthermore to enhance the process of designing suitable counter-measures. This paper provides critical analysis of induced faults on combinational and sequential circuits and study effects of various attacks (over-clock, under clock, power attack). While doing analysis, it was revealed that clock attacks i.e., under and over clock attacks have similarity index of (80–90%). Also it was found that power attacks have results similar (60–70%) to clock attacks but they cause propagation delay in circuits affecting the output. Cadence virtuoso 45 nm technology node, Keil and Multi-sim software’s were used to generate various attacks. The comparative analysis reveals that the attack timing and frequency of the glitch is the key while inducing fault injection attacks. While performing this work, it is observed the sequential circuits get less impacted by attacks comparing to combinational circuits. This research is conducted from an attacker’s perspective instead of mitigation perspective.","PeriodicalId":54866,"journal":{"name":"Journal of Circuits Systems and Computers","volume":"30 1","pages":"0"},"PeriodicalIF":0.9000,"publicationDate":"2023-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Novel Simulation Approach for Fault Injection Mechanism Assessing Dependability of Cybersecurity Attacks\",\"authors\":\"Shaminder Kaur, Ashish Sachdeva\",\"doi\":\"10.1142/s021812662450097x\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Clock attacks and power attacks are used as common means to inject faults in embedded devices. Critical analysis of the properties and the components engaged with these fault injection methods is of high importance to assess the related dangers and furthermore to enhance the process of designing suitable counter-measures. This paper provides critical analysis of induced faults on combinational and sequential circuits and study effects of various attacks (over-clock, under clock, power attack). While doing analysis, it was revealed that clock attacks i.e., under and over clock attacks have similarity index of (80–90%). Also it was found that power attacks have results similar (60–70%) to clock attacks but they cause propagation delay in circuits affecting the output. Cadence virtuoso 45 nm technology node, Keil and Multi-sim software’s were used to generate various attacks. The comparative analysis reveals that the attack timing and frequency of the glitch is the key while inducing fault injection attacks. While performing this work, it is observed the sequential circuits get less impacted by attacks comparing to combinational circuits. This research is conducted from an attacker’s perspective instead of mitigation perspective.\",\"PeriodicalId\":54866,\"journal\":{\"name\":\"Journal of Circuits Systems and Computers\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.9000,\"publicationDate\":\"2023-10-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Circuits Systems and Computers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1142/s021812662450097x\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Circuits Systems and Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1142/s021812662450097x","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

时钟攻击和功率攻击是嵌入式设备注入故障的常用手段。对这些断层注入方法所涉及的特性和部件进行严格的分析,对于评估相关危险并进一步提高设计适当对策的过程具有重要意义。本文对组合电路和顺序电路的诱发故障进行了关键分析,并研究了各种攻击(超频、欠频、功率攻击)的影响。在进行分析时,发现时钟攻击,即低于和超过时钟的攻击具有(80-90%)的相似指数。此外,还发现功率攻击的结果与时钟攻击相似(60-70%),但它们会导致影响输出的电路中的传播延迟。使用Cadence virtuoso 45纳米技术节点,Keil和Multi-sim软件生成各种攻击。对比分析表明,故障的攻击时机和频率是诱发故障注入攻击的关键。在执行这项工作时,可以观察到顺序电路受攻击的影响比组合电路小。这项研究是从攻击者的角度进行的,而不是从缓解的角度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Novel Simulation Approach for Fault Injection Mechanism Assessing Dependability of Cybersecurity Attacks
Clock attacks and power attacks are used as common means to inject faults in embedded devices. Critical analysis of the properties and the components engaged with these fault injection methods is of high importance to assess the related dangers and furthermore to enhance the process of designing suitable counter-measures. This paper provides critical analysis of induced faults on combinational and sequential circuits and study effects of various attacks (over-clock, under clock, power attack). While doing analysis, it was revealed that clock attacks i.e., under and over clock attacks have similarity index of (80–90%). Also it was found that power attacks have results similar (60–70%) to clock attacks but they cause propagation delay in circuits affecting the output. Cadence virtuoso 45 nm technology node, Keil and Multi-sim software’s were used to generate various attacks. The comparative analysis reveals that the attack timing and frequency of the glitch is the key while inducing fault injection attacks. While performing this work, it is observed the sequential circuits get less impacted by attacks comparing to combinational circuits. This research is conducted from an attacker’s perspective instead of mitigation perspective.
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来源期刊
Journal of Circuits Systems and Computers
Journal of Circuits Systems and Computers 工程技术-工程:电子与电气
CiteScore
2.80
自引率
26.70%
发文量
350
审稿时长
5.4 months
期刊介绍: Journal of Circuits, Systems, and Computers covers a wide scope, ranging from mathematical foundations to practical engineering design in the general areas of circuits, systems, and computers with focus on their circuit aspects. Although primary emphasis will be on research papers, survey, expository and tutorial papers are also welcome. The journal consists of two sections: Papers - Contributions in this section may be of a research or tutorial nature. Research papers must be original and must not duplicate descriptions or derivations available elsewhere. The author should limit paper length whenever this can be done without impairing quality. Letters - This section provides a vehicle for speedy publication of new results and information of current interest in circuits, systems, and computers. Focus will be directed to practical design- and applications-oriented contributions, but publication in this section will not be restricted to this material. These letters are to concentrate on reporting the results obtained, their significance and the conclusions, while including only the minimum of supporting details required to understand the contribution. Publication of a manuscript in this manner does not preclude a later publication with a fully developed version.
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