低工作损耗Si/ 4H-SiC异质结MOSFET及其门控隧穿效应分析

Q1 Engineering
Hang Chen, You-Run Zhang
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引用次数: 0

摘要

在模拟的基础上,首次提出了一种具有栅极控制隧穿效应的硅/碳化硅异质结双沟道金属氧化物半导体场效应晶体管(HDT-MOS)。在这种结构中,通道区域由Si制成,以利用其高通道迁移率和载流子密度。耐压区由4H-SiC制成,因此HDT-MOS具有类似于纯4H-SiC双沟mosfet (DT-MOSs)的高击穿电压(BV)。栅控隧穿效应表明,栅电压对异质结的隧穿电流有显著影响。以正VG形成的堆积层可以减小Si/SiC异质界面势垒的宽度,类似于欧姆接触中的重掺杂区域。这种较窄的屏障更容易让电子隧穿,从而产生较低的异质界面电阻。因此,在BV相近(约1770 V)的情况下,HDT-MOS的比导通电阻(non - sp)比DT-MOS降低了0.77 mΩ·cm2。由于HDT-MOS的栅极平台电压(VGP)较低且相应的变化较小(ΔVGP), HDT-MOS的栅极漏极电荷(QGD)和开关损耗分别比DT-MOS低52.14%和22.59%。HDT-MOS的优值(QGD × RON-SP)降低了61.25%。此外,异质界面电荷由于陷阱辅助隧道效应而降低了HDT-MOS的RON-SP,而异质界面陷阱则表现出相反的效果。因此,HDT-MOS结构可以显著降低SiC MOSFET的工作损耗,使器件应用于系统时温升更低。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Low working loss Si/4H–SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

A silicon (Si)/silicon carbide (4H–SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H–SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H–SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (VG) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 ​V), the specific on-state resistance (RON-SP) of HDT-MOS is reduced by 0.77 ​mΩ‧cm2 compared with that of DT-MOS. The gate-to-drain charge (QGD) and switching loss of HDT-MOS are 52.14 ​% and 22.59 ​% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (VGP) and the corresponding smaller variation (ΔVGP). The figure of merit (QGD ​× ​RON-SP) of HDT-MOS decreases by 61.25 ​%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.

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来源期刊
Journal of Electronic Science and Technology
Journal of Electronic Science and Technology Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
0.00%
发文量
1362
审稿时长
99 days
期刊介绍: JEST (International) covers the state-of-the-art achievements in electronic science and technology, including the most highlight areas: ¨ Communication Technology ¨ Computer Science and Information Technology ¨ Information and Network Security ¨ Bioelectronics and Biomedicine ¨ Neural Networks and Intelligent Systems ¨ Electronic Systems and Array Processing ¨ Optoelectronic and Photonic Technologies ¨ Electronic Materials and Devices ¨ Sensing and Measurement ¨ Signal Processing and Image Processing JEST (International) is dedicated to building an open, high-level academic journal supported by researchers, professionals, and academicians. The Journal has been fully indexed by Ei INSPEC and has published, with great honor, the contributions from more than 20 countries and regions in the world.
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