片上异构系统动态自适应调度的理论验证与硬件实现

IF 1.6 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
A. Alper Goksoy, Sahil Hassan, Anish Krishnakumar, Radu Marculescu, Ali Akoglu, Umit Y. Ogras
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引用次数: 0

摘要

特定领域的片上系统(dssoc)旨在缩小通用处理器和特定应用设计之间的差距。CPU集群支持可编程性,而针对目标域定制的硬件加速器则最大限度地减少任务执行时间和功耗。传统的操作系统(OS)调度器可能会降低dssoc的潜力,因为它们的执行时间可能比任务执行时间大几个数量级。为了解决这个问题,我们提出了一个动态自适应调度(DAS)框架,它结合了快速、低开销调度程序和复杂、高性能、开销较大的调度程序的优点。我们提出了一种新的运行时分类器,它根据系统工作负载选择更好的调度程序类型,从而提高系统性能和能量延迟积(EDP)。对五个实际流应用程序的实验表明,DAS始终优于快速、低开销和缓慢、复杂的调度器。在低数据速率下,DAS比复杂的调度器实现了1.29倍的加速和45%的EDP降低,当工作负载复杂性增加时,DAS比快速调度器实现了1.28倍的加速和37%的EDP降低。此外,我们证明了DAS框架的优越性能也适用于硬件平台,执行时间和EDP分别减少了48%和52%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip
Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler and a sophisticated, high-performance scheduler with a larger overhead. We present a novel runtime classifier that chooses the better scheduler type as a function of the system workload, leading to improved system performance and energy-delay product (EDP). Experiments with five real-world streaming applications indicate that DAS consistently outperforms fast, low-overhead, and slow, sophisticated schedulers. DAS achieves a 1.29× speedup and a 45% lower EDP than the sophisticated scheduler under low data rates and a 1.28× speedup and a 37% lower EDP than the fast scheduler when the workload complexity increases. Furthermore, we demonstrate that the superior performance of the DAS framework also applies to hardware platforms, with up to a 48% and 52% reduction in the execution time and EDP, respectively.
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来源期刊
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications Engineering-Electrical and Electronic Engineering
CiteScore
3.60
自引率
14.30%
发文量
57
审稿时长
11 weeks
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