高效率、低功耗开关运放的设计

Gurgen Grigoryan, Ani Aleksanyan, Tigran Grigoryan, Vladimir Abramyan
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引用次数: 0

摘要

集成电路设计的趋势是通过功耗和面积减小的方式。随着技术尺寸的缩小,超大规模集成电路的表面积也在不断缩小。降低功耗需要使用低功耗设计方法。提出了一种基于典型运算跨导放大器的高效率开关运放电路的设计方法。采用数字控制开关,可降低功耗。建议的SwOp采用14nm FinFET技术制造,当负载电容为5pF时,其直流增益为38.4dB,最大工作频率为11.5GHz,最差角功耗为114.48uW。该架构的功耗降低了约2倍。本文提出的结构可以集成到现代模数转换应用、高速接收机、存储系统中。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
THE DESIGN OF HIGH EFFICIENCY AND LOW POWER SWITCHED OPAMP
The tendency of design of integrated circuits (ICs) goes to through the power and area reduction way. The surface area of very-large scale integrated circuits is shrinking along with the shrinking of technological dimensions. Power reduction requires usage of low-power design methodologies. The design of Switched-Opamp (SwOp) circuit based on typical Operational Transconductance Amplifier (OTA), with high efficiency is presented. Reduction of power consumption, using digitally controlled switches, is provided. The suggested SwOp was fabricated in a 14nm FinFET technology and achieved a DC gain of 38.4dB, a maximum operating frequency of 11.5GHz and a power consumption of 114.48uW for worst corner (SS) when the load capacitor is 5pF. The power consumption of proposed architecture is reduced about two times. Structure proposed in the paper can be integrated in modern analog-to-digital conversion application, high-speed receivers, memory systems.
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