Power efficient MoS2 synaptic devices based on maxwell-wagner interfacial charging in binary oxides

Abstract Synaptic devices with tunable weight hold great promise in enabling non-von Neumann architecture for energy efficient computing. However, conventional metal-insulator-metal based two-terminal memristors share the same physical channel for both programming and reading, therefore the programming power consumption is dependent on the synaptic resistance states and can be particularly high when the memristor is in the low resistance states. Three terminal synaptic transistors, on the other hand, allow synchronous programming and reading and have been shown to possess excellent reliability. Here we present a binary oxide based three-terminal MoS 2 synaptic device, in which the channel conductance can be modulated by interfacial charges generated at the oxide interface driven by Maxwell-Wagner instability. The binary oxide stack serves both as an interfacial charge host and gate dielectrics. Both excitatory and inhibitory behaviors are experimentally realized, and the presynaptic potential polarity can be effectively controlled by engineering the oxide stacking sequence, which is a unique feature compared with existing charge-trap based synaptic devices and provides a new tuning knob for controlling synaptic device characteristics. By adopting a three-terminal transistor structure, the programming channel and reading channel are physically separated and the programming power consumption can be kept constantly low (∼50 pW) across a wide dynamic range of 10 5 . This work demonstrates a complementary metal oxide semiconductor compatible approach to build power efficient synaptic devices for artificial intelligence applications.