A 130-GHz Low-Area Power Amplifier in 40-nm CMOS

This paper presents a 130 GHz differential common-source architecture power amplifier using a 40-nm CMOS process. To ensure proper matching between the stages, except for the output, a transformer was used to achieve conjugate matching. For the output, a balun was used to match it to the maximum output load impedance. On-wafer tests showed that the maximum gain of the amplifier was 22.5 dB at 130 GHz, the 3-dB bandwidth was 15 GHz, and the output saturation power was 7.7 dBm. At a supply voltage of 1 V, the power consumption was 81 mW, and PAE was 7.1 % at a saturated output power. The chip area, excluding the pads, was 388 μm×168 μm.