A fast-locking low-reference spur cascaded PLL with gate-diffusion input-based phase detector and pulse width amplifier

ABSTRACTThis paper presents a newly proposed high-order cascaded phase-locked loop using a type-I phase-locked loop in the second stage. The type-I phase-locked loop includes a gate-diffusion-input-based phase detector and pulse width amplifier that leads to breaking the trade-off between reference spur and locking time. Moreover, a type-I phase-locked loop deploys a pulse width amplifier after a gate-diffusion-input-based phase detector with variable gain to amplify the phase error between the reference clock and the output of the voltage-controlled oscillator. The proposed architecture has been implemented in a 180-nm semiconductor laboratory CMOS technology. The proposed fifth-order cascaded phase-locked loop achieves the reference spur of -77 dBc, while the conventional first-stage charge-pump-based phase-locked loop achieves -59.7 dBc. It measures the 1.2 μs settling time, whereas conventional first stage charge-pump-based phase-locked loop measures 2.4 μs settling time. The cascaded phase-locked loop operates at 2.4 GHz output frequency, and the simulated phase noise at 1 MHz offset frequency is -105.4 dBc/Hz. It consumes 5.8 mW from a 1.8 V power supply.KEYWORDS: Phase-locked loop (PLL)cascaded PLLgate-diffusion input (GDI)Voltage-controlled oscillator (VCO)pulse width amplifier (PWA)DisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.