厚掺杂层对EBCMOS器件p型硅衬底电荷收集效率的影响

IF 0.6 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Xulei Qin, Qidong Shi, Feng Shi, Ye Li, De Song
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引用次数: 0

摘要

为了提高EBCMOS的电荷收集效率,我们预测并实验证实了电子倍增层的掺杂结构。在本研究中,我们通过模拟半导体材料中电子与固体原子的碰撞散射,结合电子在电子倍增层中的运动路径,模拟了不同掺杂策略下EBCMOS的电荷收集效率。仿真结果表明,采用层状掺杂结构减小指数强掺杂层的厚度可以优化EBCMOS中的电场分布。增强的掺杂结构直接促进了电荷收集效率的提高。根据模拟结果,制作并评价了掺杂样品。将指数高掺杂层厚度减小到0.1 μ m,可显著提高EBCMOS器件的电荷收集效率,达到86.27%。测试在7 μ m厚的p型硅衬底上进行,衬底上有1 μ m厚的折射率高掺杂层。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The Impact of a Thick-Doping-Layer on the Charge Collection Efficiency in the P-Type Silicon Substrate of EBCMOS Devices
In order to improve the charge collection efficiency of EBCMOS, we predicted and experimentally confirmed the doping structure of the electron multiplication layer. In this study, we simulate the charge collection efficiency of EBCMOS using various doping strategies by modeling the collisional scattering of electrons with solid atoms in semiconductor materials and combining the travel paths of electrons in the electron multiplication layer. The simulation findings demonstrate that the electric field distribution in EBCMOS could be optimized by using a layered doping structure to decrease the thickness of the index strongly doped layer. The enhanced doping structure directly contributes to the enhanced charge collecting efficiency. Based on the results of the simulations, doped samples were created and evaluated. The charge collection efficiency of EBCMOS devices might be significantly increased by decreasing the thickness of the index highly doped layer to 0.1 μ m, reaching 86.27%. The testing was done on a 7 μ m thick P-type silicon substrate with a 1 μ m thick index highly doped layer.
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来源期刊
Journal of Nanoelectronics and Optoelectronics
Journal of Nanoelectronics and Optoelectronics 工程技术-工程:电子与电气
自引率
16.70%
发文量
48
审稿时长
12.5 months
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