ANALYSIS OF THE ARCHITECTURE OF SUCCESSIVE APPROXIMATION REGISTER ADC AND APPROACHES TO ITS IMPROVEMENT

Successive approximation register analog-digital converters (SAR ADC) represent the majority of the ADC market for medium- to high-resolution ADCs. Modern SAR ADCs allow to ensure a sampling frequency of more than 100 MHz with a resolution of 10 to 12 bits. Features of the ADC architecture of this type: simplicity, high energy efficiency and dependency of conversion time from resolution. The two main components of a SAR ADC that affect its basic characteristics are the comparator and the digital-to-analog converter (DAC). The DAC based on a capacitor matrix is most often used. In practice, when implementing an ADC in an integrated view, when increasing the resolution, the natural increase of the chip area crystals, increase of the energy, which is consumed during the transformation, and decrease in productivity is intensified by number of technical and technological factors The work analyzes a number of modern approaches that are used to improve the characteristics of the SAR ADC in increased resolution. In particular, the segmentation of the DAC capacitor matrix or the division of the capacitor matrix into a matrix of binary weighted capacitors and a matrix of C-2C capacitors allows to reduce the range of required values of capacitor capacities and reduce the total capacity of the matrix. Due to this, in comparison with the basic architecture, when the ADC bit rate is increased, a smaller area on the crystal is required for the implementation of the matrix and higher performance is ensured. Replacing the capacitor of the most significant discharge of the matrix with an exact copy of its other part allows to reduce the energy consumed from the reference voltage source and spent on redistributing the charge between the capacitors of the matrix during conversion.