{"title":"一种可编程的g/sub / c CNN实现","authors":"D. Lim, G. Moschytz","doi":"10.1109/CNNA.1998.685390","DOIUrl":null,"url":null,"abstract":"An implementation of a programmable cellular neural network is reported. It overcomes some of the limiting characteristics and restrictions inherent in CMOS VLSI technologies, and allows an arbitrarily large continuous-time analog CNN to be built up by modularly connecting CNN chips with a modest number of cells. The template values are implemented as sets of unit and half-unit OTAs and are digitally step-wise programmable. The design incorporates an offset compensation and initialization circuit. All external input, output and control signals are electrical and digital. The design was carried out in a 0.8 /spl mu/ CMOS technology. Each cell occupies 0.78 mm/sup 2/, including all support circuitry. Matching accuracy was measured and operation was verified on numerous uncoupled and propagation-type templates.","PeriodicalId":171485,"journal":{"name":"1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A programmable g/sub m/-C CNN implementation\",\"authors\":\"D. Lim, G. Moschytz\",\"doi\":\"10.1109/CNNA.1998.685390\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An implementation of a programmable cellular neural network is reported. It overcomes some of the limiting characteristics and restrictions inherent in CMOS VLSI technologies, and allows an arbitrarily large continuous-time analog CNN to be built up by modularly connecting CNN chips with a modest number of cells. The template values are implemented as sets of unit and half-unit OTAs and are digitally step-wise programmable. The design incorporates an offset compensation and initialization circuit. All external input, output and control signals are electrical and digital. The design was carried out in a 0.8 /spl mu/ CMOS technology. Each cell occupies 0.78 mm/sup 2/, including all support circuitry. Matching accuracy was measured and operation was verified on numerous uncoupled and propagation-type templates.\",\"PeriodicalId\":171485,\"journal\":{\"name\":\"1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359)\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CNNA.1998.685390\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNNA.1998.685390","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An implementation of a programmable cellular neural network is reported. It overcomes some of the limiting characteristics and restrictions inherent in CMOS VLSI technologies, and allows an arbitrarily large continuous-time analog CNN to be built up by modularly connecting CNN chips with a modest number of cells. The template values are implemented as sets of unit and half-unit OTAs and are digitally step-wise programmable. The design incorporates an offset compensation and initialization circuit. All external input, output and control signals are electrical and digital. The design was carried out in a 0.8 /spl mu/ CMOS technology. Each cell occupies 0.78 mm/sup 2/, including all support circuitry. Matching accuracy was measured and operation was verified on numerous uncoupled and propagation-type templates.