基于DOCSIS 3.0的上游解调器频率恢复硬件建模

Suresh Kalle, F. Bui
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引用次数: 0

摘要

对于许多通信系统,频率偏移是不可避免的,因为即使不同振荡器之间的微小差异通常也足以引起这个问题。包括码间干扰(ISI)在内的其他非理想影响加剧了这一挑战。在本文中,考虑了频率恢复方案的硬件建模问题,该方案已被证明接近Cramer-Rao下界(CRLB),并且不受isi引起的偏置的影响。相关的设计和实现是在DOCSIS 3.0上行解调器的背景下进行的。为了研究理论和实际硬件级性能之间的对应关系、问题和影响,在MATLAB和Altera DSP Builder中实现了频率恢复方案,该方案提供了面向硬件的建模。通过对MATLAB和Altera DSP Builder的相应输出进行比较,得到的结果和分析结果吻合良好,支持了DOCSIS 3.0频率恢复方案的实际有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hardware modelling of frequency recovery in an upstream demodulator for DOCSIS 3.0
For many communication systems, frequency offset is inevitable, since even minute differences between different oscillators are typically sufficient to cause this problem. The challenge is exacerbated by other non-ideal effects, including intersymbol interference (ISI). In this paper, the hardware modelling issues are considered for a frequency recovery scheme that has been previously shown to approach the Cramer-Rao Lower Bound (CRLB) and is immune to ISI-induced biasing. The associated design and implementation are pursued in the context of a DOCSIS 3.0 upstream demodulator. To investigate the correspondences, with issues and implications, between theoretical and practical hardware-level performances, the frequency recovery scheme is implemented in MATLAB and Altera DSP Builder, which offers hardware-oriented modelling. The obtained results and analysis, which are performed by comparing corresponding outputs from MATLAB and Altera DSP Builder, show good match and support the practical validity of the frequency recovery scheme for DOCSIS 3.0.
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