Optimizing simulation speed of FPGA model-based synthesis

FPGA capacity is quickly outpacing designer's productivity and limiting the ability to exploit FPGA processing resources. Model-based synthesis, where a high level behavioral model is used for fast design iteration, which is then synthesizable directly into FPGA object code has been proposed as a solution. Several orders of magnitude difference in simulation speed have been observed between different variants of behavioral and model-based design tools and thus understanding and optimizing the trade between simulation speed and abstraction is critical. A dynamic level of abstraction of the model is also examined to study trades between abstraction, simulation speed and accuracy. Mathworks' HDL Coder tool, hand optimized behavioral VHDL, and vendor optimized Xilinx's System Generator are compared. Results are shown of directly synthesizable models with up to 894X simulation speedups compared to hand coded HDL simulations and 4356X speedups compared to other model-based synthesis tools.