Electrical analysis of InGaAs-based planar and tri-gate nMOSFET with S/D resistance dependencies at different drain biases

This paper studies the electrical analysis of InGaAs-based planar and tri-gate nMOSFET and the influence of the source/drain (S/D) resistance, Rsd on the current-voltage (${\text{I}}_{\text{d}}-{\text{V}}_{\text{g}}$) relation at different drain biases (${\text{V}}_{\text{ds}}$). It is found that the tri-gate nMOSFET simulated at high Vds has shown better performance compared to planar nMOSFET simulated at low Vds. As the Rsd is reduced, the drain current of both planar and tri-gate devices increases. The on-current to off-current (${\text{I}}_{\text{on}})/{\text{I}}_{\text{off}}$) ratio of the devices also increases as the Rsd reduced. Tri-gate nMOSFET shows significant improvement as the Ion/Ioff ratio is $10^{3}$ higher than the planar nMOSFET device.