分析图形处理器单元(GPU)指令集体系结构

2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) Pub Date : 2015-03-29 DOI:10.1109/ISPASS.2015.7095794

Kothiya Mayank, Hongwen Dai, Jizeng Wei, Huiyang Zhou

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引用次数: 3

摘要

由于它们的高吞吐量和高能效，像图形处理单元(gpu)这样的大规模并行体系结构成为广泛用途计算的流行平台。然而，尽管众所周知，GPU指令集架构是包括GPU在内的所有现代处理器的基本设计问题，但对GPU指令集架构的研究和分析却很少。

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Analyzing graphics processor unit (GPU) instruction set architectures

Because of their high throughput and power efficiency, massively parallel architectures like graphics processing units (GPUs) become a popular platform for generous purpose computing. However, there are few studies and analyses on GPU instruction set architectures (ISAs) although it is wellknown that the ISA is a fundamental design issue of all modern processors including GPUs.

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2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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