{"title":"用于块级动态电压缩放的片上DC-DC变换器设计要求","authors":"M. Ichihashi","doi":"10.1109/RME.2009.5201374","DOIUrl":null,"url":null,"abstract":"This paper discusses the design requirement of on-chip dc-dc converter for block-level Dynamic Voltage Scaling (DVS). The target application is low-power SoC where DVS can be applied to all the implemented logic blocks. The proposed converter occupies only five bonding pads and the simulation demonstrates that the leakage current is only 84 nA in the standby mode. As shown by a set of equations based on a first order model, the proposed converter does not need any pulse frequency modulator (PFM).","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"118 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design requirement of on-chip DC-DC converter for block-level Dynamic Voltage Scaling\",\"authors\":\"M. Ichihashi\",\"doi\":\"10.1109/RME.2009.5201374\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses the design requirement of on-chip dc-dc converter for block-level Dynamic Voltage Scaling (DVS). The target application is low-power SoC where DVS can be applied to all the implemented logic blocks. The proposed converter occupies only five bonding pads and the simulation demonstrates that the leakage current is only 84 nA in the standby mode. As shown by a set of equations based on a first order model, the proposed converter does not need any pulse frequency modulator (PFM).\",\"PeriodicalId\":245992,\"journal\":{\"name\":\"2009 Ph.D. Research in Microelectronics and Electronics\",\"volume\":\"118 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Ph.D. Research in Microelectronics and Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2009.5201374\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Ph.D. Research in Microelectronics and Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2009.5201374","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design requirement of on-chip DC-DC converter for block-level Dynamic Voltage Scaling
This paper discusses the design requirement of on-chip dc-dc converter for block-level Dynamic Voltage Scaling (DVS). The target application is low-power SoC where DVS can be applied to all the implemented logic blocks. The proposed converter occupies only five bonding pads and the simulation demonstrates that the leakage current is only 84 nA in the standby mode. As shown by a set of equations based on a first order model, the proposed converter does not need any pulse frequency modulator (PFM).
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