基于ai的物联网边缘设备的低主备功耗0.23V 40nm OAI-ROM

2020 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2020-01-01 DOI:10.1109/ICEIC49074.2020.9051040

Jinn-Shyan Wang, Cheng-Xin Xue, Chien-Tung Liu, Tay-Jyi Lin

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引用次数: 0

摘要

亚阈值(sub-Vt) ROM是基于人工智能的物联网设备(如声控边缘计算soc)中的代码存储元件。降低待机功率以延长电池寿命和提高运行速度以提高响应速度是亚vt ROM的两个设计追求。传统的NAND-ROM使用额外的基于代码反转的标志表来提高速度，但牺牲泄漏。在这项工作中，我们提出了OAI-ROM来提高速度，而不使用标志表来减少泄漏。该ROM采用交错屏蔽方案来避免串扰，并采用自适应泄漏补偿来实现可变弹性的亚vt工作。40nm OAI-ROM的最小电源电压为0.23V，与采用相同CMOS重新设计的NAND-ROM相比，其工作功率和待机功率分别降低23%和88%，速度提高1.67倍。

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A 0.23V 40nm OAI-ROM with Low Active and Standby Power for AI-based IoT Edge Devices

Sub-threshold (sub-Vt) ROM is the code storage element in AI-based IoT devices, such as voice-activated edge-computing SoCs. Reducing standby power for longer battery life and improving operating speed for faster response are two design pursuits for sub-Vt ROM. A conventional NAND-ROM used an extra code-inversion-based flag-table for enhancing speed but sacrificing leakage. In this work, we propose OAI-ROM to improve speed without using the flag-table for leakage reduction. The proposed ROM adopts the interleaved-shielding scheme to avoid crosstalk and the adaptive leakage compensation to achieve variation-resilient sub-Vt operation. The 40nm OAI-ROM has a minimum supply voltage of 0.23V with 23% and 88% less active and standby power, respectively, and 1.67 times higher speed compared to the NAND-ROM redesigned in the same CMOS.

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来源期刊

2020 International Conference on Electronics, Information, and Communication (ICEIC)

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