Amit V. Patel, Jitendra P. Chaudhari, Alpesh Vala, Hiren K. Mewada, Keyur K. Mahant, Jawad F. Al-Asad
{"title":"基于0.18µm CMOS技术的宽带LNA","authors":"Amit V. Patel, Jitendra P. Chaudhari, Alpesh Vala, Hiren K. Mewada, Keyur K. Mahant, Jawad F. Al-Asad","doi":"10.1109/ISAECT53699.2021.9668493","DOIUrl":null,"url":null,"abstract":"This paper represents the 0.18 µm CMOS technology-based implementation of wideband (0.1 - 4 GHz) LNA for cellular services, terrestrial communication and satellite navigation. Here, a wideband operation is achieved by the design of the current reuse methodology and negative feedback between the drain and gate terminal of the device to be operated in a common source (CS) configuration. The proposed design improves the transconductance and reduces the drain current by half due to the scaling of the device geometry using the W/L ratio. The implanted design provides greater than 30 dB gain in three cascaded stages with input-output return loss better than -12 dB throughout the band and a noise figure less than 3 dB. The formulated design consumes 18 mA power from a 1.8 V source.","PeriodicalId":137636,"journal":{"name":"2021 4th International Symposium on Advanced Electrical and Communication Technologies (ISAECT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Wideband LNA in 0.18 µm CMOS Technology\",\"authors\":\"Amit V. Patel, Jitendra P. Chaudhari, Alpesh Vala, Hiren K. Mewada, Keyur K. Mahant, Jawad F. Al-Asad\",\"doi\":\"10.1109/ISAECT53699.2021.9668493\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper represents the 0.18 µm CMOS technology-based implementation of wideband (0.1 - 4 GHz) LNA for cellular services, terrestrial communication and satellite navigation. Here, a wideband operation is achieved by the design of the current reuse methodology and negative feedback between the drain and gate terminal of the device to be operated in a common source (CS) configuration. The proposed design improves the transconductance and reduces the drain current by half due to the scaling of the device geometry using the W/L ratio. The implanted design provides greater than 30 dB gain in three cascaded stages with input-output return loss better than -12 dB throughout the band and a noise figure less than 3 dB. The formulated design consumes 18 mA power from a 1.8 V source.\",\"PeriodicalId\":137636,\"journal\":{\"name\":\"2021 4th International Symposium on Advanced Electrical and Communication Technologies (ISAECT)\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-12-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 4th International Symposium on Advanced Electrical and Communication Technologies (ISAECT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISAECT53699.2021.9668493\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 4th International Symposium on Advanced Electrical and Communication Technologies (ISAECT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISAECT53699.2021.9668493","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper represents the 0.18 µm CMOS technology-based implementation of wideband (0.1 - 4 GHz) LNA for cellular services, terrestrial communication and satellite navigation. Here, a wideband operation is achieved by the design of the current reuse methodology and negative feedback between the drain and gate terminal of the device to be operated in a common source (CS) configuration. The proposed design improves the transconductance and reduces the drain current by half due to the scaling of the device geometry using the W/L ratio. The implanted design provides greater than 30 dB gain in three cascaded stages with input-output return loss better than -12 dB throughout the band and a noise figure less than 3 dB. The formulated design consumes 18 mA power from a 1.8 V source.