RISC处理器的VHDL自顶向下建模

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410676

H. Juan, N. D. Holmes, Smita Bakshi, D. Gajski

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引用次数: 11

摘要

作者提出了一种具有三个建模级别的高级设计建模方法:规范级别、接口级别和功能级别。他们在RISC处理器设计上演示了该方法。所有模型都在VHDL中实现，并在SPARC 1工作站上使用ZYCAD VHDL模拟器1.0a进行仿真。实验结果证明了该方法的可行性和有效性

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Top-down modeling of RISC processors in VHDL

The authors present a high-level design modeling methodology with three modeling levels: a specification level, an interface level, and a functional level. They demonstrate the methodology on a RISC processor design. All models have been implemented in VHDL and simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results demonstrate the feasibility and usefulness of the methodology.<>

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来源期刊

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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