FPGA Implementation of FEC Encoder with BCH & LDPC Codes for DVB S2 System

This paper gives the design and implementation of Xilinx FPGA based Forward Error Correction (FEC) encoder for DVB S2 system which includes BCH code followed by LDPC code and finally bit mapped to constellation for QPSK modulation. DVB-S2 FEC: ($\mathbf{n}=64800,\ \mathbf{k}=32400$) rate 1/2 code, with QPSK modulation scheme is considered as target for FPGA implementation. The architecture in this design efficiently uses pipeline technique along with parallel processing to optimize the hardware resources and overall latency, to accomplish FEC encoding for DVB S2 system. Coding is completed in Verilog HDL with Xilinx Virtex6 XC6VLX240T FPGA as target for hardware realization and QuestaSim simulator is used to complete the functional simulation.