基于FPGA硬件的高频交易低延迟库

J. Lockwood, Adwait Gupte, Nishit Mehta, Michaela Blott, T. English, K. Vissers
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引用次数: 77

摘要

当前的高频交易(HFT)平台通常是在具有高性能网络适配器的计算机上的软件中实现的。这些系统的高且不可预测的延迟导致交易世界探索具有硬件加速的替代“混合”架构。在本文中,我们调查了现有的解决方案,并描述了如何在电子交易中使用fpga来接近零延迟的目标。我们提出了一个FPGA IP库,实现了网络、I/O、内存接口和金融协议解析器。该图书馆提供了预先构建的基础设施,加速了新的金融应用程序的开发和验证。我们在定制的1U FPGA设备上使用IP库开发了一个示例金融应用程序。该应用程序支持10Gb/s以太网线路速率,端到端固定延迟为1μs,比同类软件实现低两个数量级。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT)
Current High-Frequency Trading (HFT) platforms are typically implemented in software on computers with high-performance network adapters. The high and unpredictable latency of these systems has led the trading world to explore alternative "hybrid" architectures with hardware acceleration. In this paper, we survey existing solutions and describe how FPGAs are being used in electronic trading to approach the goal of zero latency. We present an FPGA IP library which implements networking, I/O, memory interfaces and financial protocol parsers. The library provides pre-built infrastructure which accelerates the development and verification of new financial applications. We have developed an example financial application using the IP library on a custom 1U FPGA appliance. The application sustains 10Gb/s Ethernet line rate with a fixed end-to-end latency of 1μs - up to two orders of magnitude lower than comparable software implementations.
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