{"title":"采用进化计算优化数据路径设计","authors":"Sérgio G. Araújo, A. C. M. Filho, A. Pedroza","doi":"10.1109/IWSOC.2003.1212996","DOIUrl":null,"url":null,"abstract":"High-level design entry tools offer a nice framework to deal with today's complex systems while shortening the design cycle. Nevertheless, such tools provide poor quality results both in area usage and timing performance issues. This paper presents a methodology to design optimized datapaths based on evolutionary techniques and HLS tools. VHDL descriptions of the system are automatically generated by Genetic Programming. To improve the design of the structural quality of such descriptions, a two-stage multi-objective optimization algorithm is used to ensure both desired functionality and area constraints.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Optimized datapath design by evolutionary computation\",\"authors\":\"Sérgio G. Araújo, A. C. M. Filho, A. Pedroza\",\"doi\":\"10.1109/IWSOC.2003.1212996\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-level design entry tools offer a nice framework to deal with today's complex systems while shortening the design cycle. Nevertheless, such tools provide poor quality results both in area usage and timing performance issues. This paper presents a methodology to design optimized datapaths based on evolutionary techniques and HLS tools. VHDL descriptions of the system are automatically generated by Genetic Programming. To improve the design of the structural quality of such descriptions, a two-stage multi-objective optimization algorithm is used to ensure both desired functionality and area constraints.\",\"PeriodicalId\":259178,\"journal\":{\"name\":\"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.\",\"volume\":\"136 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-07-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2003.1212996\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2003.1212996","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimized datapath design by evolutionary computation
High-level design entry tools offer a nice framework to deal with today's complex systems while shortening the design cycle. Nevertheless, such tools provide poor quality results both in area usage and timing performance issues. This paper presents a methodology to design optimized datapaths based on evolutionary techniques and HLS tools. VHDL descriptions of the system are automatically generated by Genetic Programming. To improve the design of the structural quality of such descriptions, a two-stage multi-objective optimization algorithm is used to ensure both desired functionality and area constraints.