{"title":"同步数字系统卡滞故障仿真新方法","authors":"L. Tung, M. Mills","doi":"10.1145/41824.41826","DOIUrl":null,"url":null,"abstract":"A new approach is proposed for stuck-at fault simulations. Stuck-at fault models in the approach are developed via the component connection model. Based on the approach, a simulation program is designed. A combinational logic circuit is simulated and the test sets are generated using the program.","PeriodicalId":186490,"journal":{"name":"Annual Simulation Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1987-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A new approach of stuck-at fault simulation for synchronous digital systems\",\"authors\":\"L. Tung, M. Mills\",\"doi\":\"10.1145/41824.41826\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new approach is proposed for stuck-at fault simulations. Stuck-at fault models in the approach are developed via the component connection model. Based on the approach, a simulation program is designed. A combinational logic circuit is simulated and the test sets are generated using the program.\",\"PeriodicalId\":186490,\"journal\":{\"name\":\"Annual Simulation Symposium\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1987-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Annual Simulation Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/41824.41826\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Annual Simulation Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/41824.41826","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new approach of stuck-at fault simulation for synchronous digital systems
A new approach is proposed for stuck-at fault simulations. Stuck-at fault models in the approach are developed via the component connection model. Based on the approach, a simulation program is designed. A combinational logic circuit is simulated and the test sets are generated using the program.