多芯片封装中高速封装互连的串扰研究

B. E. Cheah, J. Kong, K. Yong, L. Lo, Po Yin Yaw
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引用次数: 2

摘要

本文研究了多芯片封装(MCP)中高速封装内互连的串扰分析。本研究探讨了相邻攻击者的串扰耦合效应对信号性能的影响,如睁眼和信号超调。在2Gbps到6Gbps的微带和带状线结构上进行了仿真。进一步探讨了封装走线宽度、走线间距比以及通道长度等关键设计参数,确定了高速封装上互连设计中串扰耦合的主导因素。仿真结果表明,二阶以上相邻干扰源的串扰效应对信号性能仍有较大影响,需要在高速MCP应用中慎重考虑。本文还建立了一些指导方针,以实现信号性能和硅房地产之间的最佳设计权衡。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Crosstalk study of high speed on-package interconnects for multi-chip package
This paper presents the crosstalk analysis study for high-speed on-package interconnects in multi-chip package (MCP). The crosstalk coupling effects from adjacent aggressors on signaling performance e.g. eye opening and signal overshoot were investigated in this study. Simulations were performed on both microstrip and stripline structures from 2Gbps up-to 6Gbps. Several key design parameters e.g. package trace width and trace spacing ratio as well as the channel length were further explored to identify the dominating factor of crosstalk coupling in the high-speed on-package interconnect design. Simulation results indicated the crosstalk effects from adjacent aggressors beyond second order still have significant impacts on the signaling performance and need to be carefully considered for high-speed MCP applications. This paper also establishes several guidelines to enable optimum design trade-off between signaling performance and silicon real-estate.
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