一种有源电感双环频率合成器的设计

S. Sinha, M. du Plessis
{"title":"一种有源电感双环频率合成器的设计","authors":"S. Sinha, M. du Plessis","doi":"10.1109/EDMO.2004.1412399","DOIUrl":null,"url":null,"abstract":"High costs, bulkiness, and larger power consumption makes transceiver integration and miniaturization a desired option to discretely implemented transceivers. Furthermore, a frequency synthesizer forms an important part of high-frequency transceivers. In this paper, the design of a fully-integrated dual loop frequency synthesizer is detailed. Previously, frequency synthesizers have already been implemented using CMOS technology. The synthesizer discussed in this paper deploys a dual loop architecture with a high-frequency LC voltage controlled oscillator (VCO) forming part of one of the loops. As opposed to previous architectures, the synthesizer discussed in this paper utilises an active-inductor LC VCO as opposed to a passive-inductor LC VCO deployed in earlier synthesizer implementations. Amongst others, an important advantage of this implementation is the higher quality, Q-factor of the active inductor at the trade-off of increased noise and power dissipation. The synthesizer generates signals in the microwave frequency (2.4-2.5 GHz) range with a 1 MHz resolution. Using the 0.35 /spl mu/m BiCMOS process, simulations showed a phase noise of -117 dBc/Hz at an offset of 1 MHz and reference sidebands at -80 dBc, both these parameters with respect to a 2.45 GHz carrier.","PeriodicalId":424447,"journal":{"name":"12th International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2004. EDMO 2004.","volume":"330 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of an active-inductor dual-loop frequency synthesizer\",\"authors\":\"S. Sinha, M. du Plessis\",\"doi\":\"10.1109/EDMO.2004.1412399\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High costs, bulkiness, and larger power consumption makes transceiver integration and miniaturization a desired option to discretely implemented transceivers. Furthermore, a frequency synthesizer forms an important part of high-frequency transceivers. In this paper, the design of a fully-integrated dual loop frequency synthesizer is detailed. Previously, frequency synthesizers have already been implemented using CMOS technology. The synthesizer discussed in this paper deploys a dual loop architecture with a high-frequency LC voltage controlled oscillator (VCO) forming part of one of the loops. As opposed to previous architectures, the synthesizer discussed in this paper utilises an active-inductor LC VCO as opposed to a passive-inductor LC VCO deployed in earlier synthesizer implementations. Amongst others, an important advantage of this implementation is the higher quality, Q-factor of the active inductor at the trade-off of increased noise and power dissipation. The synthesizer generates signals in the microwave frequency (2.4-2.5 GHz) range with a 1 MHz resolution. Using the 0.35 /spl mu/m BiCMOS process, simulations showed a phase noise of -117 dBc/Hz at an offset of 1 MHz and reference sidebands at -80 dBc, both these parameters with respect to a 2.45 GHz carrier.\",\"PeriodicalId\":424447,\"journal\":{\"name\":\"12th International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2004. EDMO 2004.\",\"volume\":\"330 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"12th International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2004. EDMO 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDMO.2004.1412399\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2004. EDMO 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDMO.2004.1412399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

高成本、体积和较大的功耗使得收发器集成和小型化成为离散实现收发器的理想选择。此外,频率合成器是高频收发器的重要组成部分。本文详细介绍了一种全集成双环频率合成器的设计。以前,频率合成器已经使用CMOS技术实现。本文讨论的合成器采用双环结构,高频LC压控振荡器(VCO)构成其中一个环的一部分。与以前的架构相反,本文讨论的合成器使用有源电感LC VCO,而不是在早期的合成器实现中部署的无源电感LC VCO。除其他外,这种实现的一个重要优点是在增加噪声和功耗的代价下,有源电感的质量更高,q因子更高。合成器产生的信号在微波频率(2.4-2.5 GHz)范围内,分辨率为1mhz。使用0.35 /spl mu/m的BiCMOS工艺,仿真结果表明,相对于2.45 GHz载波,在偏移1 MHz时相位噪声为-117 dBc/Hz,参考边带为-80 dBc。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of an active-inductor dual-loop frequency synthesizer
High costs, bulkiness, and larger power consumption makes transceiver integration and miniaturization a desired option to discretely implemented transceivers. Furthermore, a frequency synthesizer forms an important part of high-frequency transceivers. In this paper, the design of a fully-integrated dual loop frequency synthesizer is detailed. Previously, frequency synthesizers have already been implemented using CMOS technology. The synthesizer discussed in this paper deploys a dual loop architecture with a high-frequency LC voltage controlled oscillator (VCO) forming part of one of the loops. As opposed to previous architectures, the synthesizer discussed in this paper utilises an active-inductor LC VCO as opposed to a passive-inductor LC VCO deployed in earlier synthesizer implementations. Amongst others, an important advantage of this implementation is the higher quality, Q-factor of the active inductor at the trade-off of increased noise and power dissipation. The synthesizer generates signals in the microwave frequency (2.4-2.5 GHz) range with a 1 MHz resolution. Using the 0.35 /spl mu/m BiCMOS process, simulations showed a phase noise of -117 dBc/Hz at an offset of 1 MHz and reference sidebands at -80 dBc, both these parameters with respect to a 2.45 GHz carrier.
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