{"title":"自组织网络数字信号重采样装置","authors":"E. Voronov, Alexey Solodkov, E. Belousov","doi":"10.1109/ITECHA.2015.7317386","DOIUrl":null,"url":null,"abstract":"This paper presents a device that resamples a digital signal and which is based on a hardware-software complex (HSC) of a secure communication channel for self-organizing networks. In addition, the development of a model of the resampling device in MATLAB Simulink and its description in Verilog will be discussed. Furthermore the results of simulations of the device in Xilinx ISim are shown, as well as the waveform of original and resampled signals after device implementation on a FPGA Xilinx Virtex-4 XC4VFX12.","PeriodicalId":161782,"journal":{"name":"2015 Internet Technologies and Applications (ITA)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Digital signal resampling device for self-organizing networks\",\"authors\":\"E. Voronov, Alexey Solodkov, E. Belousov\",\"doi\":\"10.1109/ITECHA.2015.7317386\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a device that resamples a digital signal and which is based on a hardware-software complex (HSC) of a secure communication channel for self-organizing networks. In addition, the development of a model of the resampling device in MATLAB Simulink and its description in Verilog will be discussed. Furthermore the results of simulations of the device in Xilinx ISim are shown, as well as the waveform of original and resampled signals after device implementation on a FPGA Xilinx Virtex-4 XC4VFX12.\",\"PeriodicalId\":161782,\"journal\":{\"name\":\"2015 Internet Technologies and Applications (ITA)\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Internet Technologies and Applications (ITA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITECHA.2015.7317386\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Internet Technologies and Applications (ITA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITECHA.2015.7317386","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Digital signal resampling device for self-organizing networks
This paper presents a device that resamples a digital signal and which is based on a hardware-software complex (HSC) of a secure communication channel for self-organizing networks. In addition, the development of a model of the resampling device in MATLAB Simulink and its description in Verilog will be discussed. Furthermore the results of simulations of the device in Xilinx ISim are shown, as well as the waveform of original and resampled signals after device implementation on a FPGA Xilinx Virtex-4 XC4VFX12.
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