Design automation of analog module using hierarchical decomposition

In this paper a methodology for design automation of bigger analog module is proposed. The proposed methodology uses hierarchical decomposition of the bigger module into its constituents cell level circuits (referred to as leaf cells) and then the cell level circuits are designed using top down constraint driven design approach. This hierarchical decomposition reduces the complexity of the design automation task. The trade-off characteristic curves of the cell level circuits are used to determine the design feasibility and to propagate the specification of the bigger module to that of its constituent leaf cells. The methodology is validated in a 0.18 μm CMOS process by designing a highperformance gain boosted folded cascode Op-Amp (GBOPAMP) for the first stage of a 10-bit 50 Ms/s pipeline ADC. The designed GBOPAMP achieves a DC gain of 75 dB, a unity-gain frequency (UGF) of 520 MHz with 65° phase margin and a 0.09 % settling time of 6.5 ns. Complete design of the GBOPAMP takes less than 10 mins using an Intel Core 2 Duo, 2.53 GHz processor.