T. Koizumi, Takeo Owada, M. Motoyoshi, S. Kameda, N. Suematsu
{"title":"用于直接射频欠采样接收机的0.4 ns功率开关ku波段放大器","authors":"T. Koizumi, Takeo Owada, M. Motoyoshi, S. Kameda, N. Suematsu","doi":"10.1109/GSMM.2016.7500296","DOIUrl":null,"url":null,"abstract":"We have developed a high speed gate switching type Ku-band CMOS amplifier for direct RF undersampling receiver. This amplifier will synchronize its d.c. power switch timing to the sampling clock of the direct RF undersampling receiver. For Ku-band VSAT application, we designed the sampling clock frequency of undersampling receiver as 600 MHz, therefore the power switching time (Turn-On Time) of less than 0.83 ns is required. By using gate bias switching configuration, we achieve 0.4 ns power switching time by both simulation and measurement. This high speed power switching amplifier enable to reduce the d.c. power consumption about 1/2 when the 50% duty cycle of the clock for switching is applied.","PeriodicalId":156809,"journal":{"name":"2016 Global Symposium on Millimeter Waves (GSMM) & ESA Workshop on Millimetre-Wave Technology and Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 0.4-ns power switching Ku-band amplifier for direct RF undersampling receiver\",\"authors\":\"T. Koizumi, Takeo Owada, M. Motoyoshi, S. Kameda, N. Suematsu\",\"doi\":\"10.1109/GSMM.2016.7500296\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have developed a high speed gate switching type Ku-band CMOS amplifier for direct RF undersampling receiver. This amplifier will synchronize its d.c. power switch timing to the sampling clock of the direct RF undersampling receiver. For Ku-band VSAT application, we designed the sampling clock frequency of undersampling receiver as 600 MHz, therefore the power switching time (Turn-On Time) of less than 0.83 ns is required. By using gate bias switching configuration, we achieve 0.4 ns power switching time by both simulation and measurement. This high speed power switching amplifier enable to reduce the d.c. power consumption about 1/2 when the 50% duty cycle of the clock for switching is applied.\",\"PeriodicalId\":156809,\"journal\":{\"name\":\"2016 Global Symposium on Millimeter Waves (GSMM) & ESA Workshop on Millimetre-Wave Technology and Applications\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 Global Symposium on Millimeter Waves (GSMM) & ESA Workshop on Millimetre-Wave Technology and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GSMM.2016.7500296\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 Global Symposium on Millimeter Waves (GSMM) & ESA Workshop on Millimetre-Wave Technology and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GSMM.2016.7500296","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.4-ns power switching Ku-band amplifier for direct RF undersampling receiver
We have developed a high speed gate switching type Ku-band CMOS amplifier for direct RF undersampling receiver. This amplifier will synchronize its d.c. power switch timing to the sampling clock of the direct RF undersampling receiver. For Ku-band VSAT application, we designed the sampling clock frequency of undersampling receiver as 600 MHz, therefore the power switching time (Turn-On Time) of less than 0.83 ns is required. By using gate bias switching configuration, we achieve 0.4 ns power switching time by both simulation and measurement. This high speed power switching amplifier enable to reduce the d.c. power consumption about 1/2 when the 50% duty cycle of the clock for switching is applied.