DAC用于正电子发射断层成像前端

H. Cruz, Ting-Chia Yeh, Hong-Yi Huang, Shueen-Yu Lee, C. Luo
{"title":"DAC用于正电子发射断层成像前端","authors":"H. Cruz, Ting-Chia Yeh, Hong-Yi Huang, Shueen-Yu Lee, C. Luo","doi":"10.1109/ISBB.2014.6820890","DOIUrl":null,"url":null,"abstract":"Positron emission tomography architectures have been traditionally dependent on zero crossing discriminators, external voltage references, or fixed voltage references with restricted voltage steps. This paper presents a digital-to-analog converter (DAC) utilized to set the threshold voltages of Time-of-Flight Positron Emission Tomography (TOF-PET) comparators. The DAC circuit uses a charge redistribution architecture, and all the required building blocks have been fully integrated in a 90 nm CMOS process with an area of 170 × 65 μm2. The power consumption is 324 μW with 1.2-V supply voltage. Using a 10-MHz clock, this DAC achieves an effective number of bits (ENOB) of 8.2.","PeriodicalId":265886,"journal":{"name":"2014 IEEE International Symposium on Bioelectronics and Bioinformatics (IEEE ISBB 2014)","volume":"58 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"DAC for positron emission tomography front-end\",\"authors\":\"H. Cruz, Ting-Chia Yeh, Hong-Yi Huang, Shueen-Yu Lee, C. Luo\",\"doi\":\"10.1109/ISBB.2014.6820890\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Positron emission tomography architectures have been traditionally dependent on zero crossing discriminators, external voltage references, or fixed voltage references with restricted voltage steps. This paper presents a digital-to-analog converter (DAC) utilized to set the threshold voltages of Time-of-Flight Positron Emission Tomography (TOF-PET) comparators. The DAC circuit uses a charge redistribution architecture, and all the required building blocks have been fully integrated in a 90 nm CMOS process with an area of 170 × 65 μm2. The power consumption is 324 μW with 1.2-V supply voltage. Using a 10-MHz clock, this DAC achieves an effective number of bits (ENOB) of 8.2.\",\"PeriodicalId\":265886,\"journal\":{\"name\":\"2014 IEEE International Symposium on Bioelectronics and Bioinformatics (IEEE ISBB 2014)\",\"volume\":\"58 4\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Symposium on Bioelectronics and Bioinformatics (IEEE ISBB 2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISBB.2014.6820890\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Symposium on Bioelectronics and Bioinformatics (IEEE ISBB 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISBB.2014.6820890","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

传统上,正电子发射层析成像结构依赖于零交叉鉴别器、外部电压参考或具有限制电压阶跃的固定电压参考。本文提出了一种用于设定飞行时间正电子发射断层扫描(TOF-PET)比较器阈值电压的数模转换器(DAC)。DAC电路采用电荷再分配架构,所有所需的构建模块都完全集成在面积为170 × 65 μm2的90 nm CMOS工艺中。电源电压为1.2 v时,功耗为324 μW。使用10-MHz时钟,该DAC实现8.2的有效位数(ENOB)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
DAC for positron emission tomography front-end
Positron emission tomography architectures have been traditionally dependent on zero crossing discriminators, external voltage references, or fixed voltage references with restricted voltage steps. This paper presents a digital-to-analog converter (DAC) utilized to set the threshold voltages of Time-of-Flight Positron Emission Tomography (TOF-PET) comparators. The DAC circuit uses a charge redistribution architecture, and all the required building blocks have been fully integrated in a 90 nm CMOS process with an area of 170 × 65 μm2. The power consumption is 324 μW with 1.2-V supply voltage. Using a 10-MHz clock, this DAC achieves an effective number of bits (ENOB) of 8.2.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信