Applied Modeling Framework in Integrated Circuit Design and Reliability

A complete analysis was presented to improve the reliability of microelectronics packages by providing numerical models that are sufficiently precise to predict product reliability for relevant defects and failure modes in microelectronics packaging such as module warpage, solder fatigue cracking, TIM tearing or delamination and underfill corner cracking causing chip circuits delamination and increased flip chip solder joint fatigue. The numerical simulations were performed using a specialized cloud software infrastructure named PACK using a one-way macro to micro model approach. Model validation was split into two main aspects. First, the linear behavior of the macro model was based on bottom surface metallurgy (BSM) warpage. BSM module warpage of several packages from ICOS data was used to validate the numerical model, and both room temperature warpage as well as the shape predicted by the FEM model agreed with the ICOS data. Second, the fatigue modeling accuracy was evaluated based on data issued from devices built and subjected to thermal cycles akin to the models. The non-linear simulation of creep was then performed using Norton’s creep model, using SAC material properties obtained from experimental sources. The strain energy density (SEND) was used as a metric to quantify solder creep and interconnect fatigue. The SEND was averaged over a few layers of elements at the top and bottom of the interconnects, forming a normalized volume where creep (and failure probability) was the highest. Early thermal cycles solder fatigue fails were detected electrically on the prototypes, located on the memory module’s corners. These observations were confirmed with dye and pry which corresponded with the computed SEND map and distribution given by the numerical model. Failure analysis (FA) showed that cracks initiated near the bottom side pad neck and propagating along the BGA which was also in agreement with the modeled metric’s distribution across critical BGAs. Finally, laminate BGA resin cracking fail was found under the shadow of a silicon die. Laminate BSM solder mask von Mises stress mapping was shown to be predictive of the critical locations where delamination and Cu line cracking was observed. In conclusion, the study was able to leverage available reliability stress data to calibrate the numerical model and set reference baseline while providing IBM development team guidance to narrow down the selection of best reliable lower cost package configurations for qualification decision, demonstrating the effectiveness of our modeling platform to predict module warpage despite the complexity of the package and the failure modes encountered in the design and manufacture of microelectronics packaging.