{"title":"用于Q/ v波段卫星通信的40nm CMOS Q波段低噪声放大器","authors":"Qin Tian, Dixian Zhao","doi":"10.1109/ICTA56932.2022.9963129","DOIUrl":null,"url":null,"abstract":"This paper proposes a Q-band single-ended LNA fabricated in 40-nm CMOS technology, where two-stage cascode topology and inductive source degeneration technique are employed. The proposed LNA has achieved a lowest NF of 4.3 dB, and a maximum power gain of 24.2 dB with a 3-dB bandwidth of 11 GHz, consuming 17.85 mW dc power from a 1.5 V supply.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Q-Band Low-Noise Amplifier in 40-nm CMOS for Q/V-band satellite communications\",\"authors\":\"Qin Tian, Dixian Zhao\",\"doi\":\"10.1109/ICTA56932.2022.9963129\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a Q-band single-ended LNA fabricated in 40-nm CMOS technology, where two-stage cascode topology and inductive source degeneration technique are employed. The proposed LNA has achieved a lowest NF of 4.3 dB, and a maximum power gain of 24.2 dB with a 3-dB bandwidth of 11 GHz, consuming 17.85 mW dc power from a 1.5 V supply.\",\"PeriodicalId\":325602,\"journal\":{\"name\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICTA56932.2022.9963129\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9963129","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Q-Band Low-Noise Amplifier in 40-nm CMOS for Q/V-band satellite communications
This paper proposes a Q-band single-ended LNA fabricated in 40-nm CMOS technology, where two-stage cascode topology and inductive source degeneration technique are employed. The proposed LNA has achieved a lowest NF of 4.3 dB, and a maximum power gain of 24.2 dB with a 3-dB bandwidth of 11 GHz, consuming 17.85 mW dc power from a 1.5 V supply.