{"title":"基于CORDIC元件的可重构DSP板","authors":"E. Mariatos, M. Birbas, A. Birbas","doi":"10.1109/IWRSP.1994.315899","DOIUrl":null,"url":null,"abstract":"In this paper, a reconfigurable rapid prototyping system, oriented to DSP applications is proposed. Using the novel approach of combining the reconfigurability offered by an FPGA unit and the processing power of the CORDIC architecture, a fast, scalable and highly parallel structure has been developed. The results obtained by experimenting with the implementation of DCT algorithms are really promising, in terms of performance and versatility, which allows us to proceed for the development of a prototype that will be targeted to an image compression standard like H.261. Moreover, it is envisioned to build a parametrised library of hardware compilers that will map a wide range of DSP algorithms on the proposed board.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A reconfigurable DSP board based on CORDIC elements\",\"authors\":\"E. Mariatos, M. Birbas, A. Birbas\",\"doi\":\"10.1109/IWRSP.1994.315899\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a reconfigurable rapid prototyping system, oriented to DSP applications is proposed. Using the novel approach of combining the reconfigurability offered by an FPGA unit and the processing power of the CORDIC architecture, a fast, scalable and highly parallel structure has been developed. The results obtained by experimenting with the implementation of DCT algorithms are really promising, in terms of performance and versatility, which allows us to proceed for the development of a prototype that will be targeted to an image compression standard like H.261. Moreover, it is envisioned to build a parametrised library of hardware compilers that will map a wide range of DSP algorithms on the proposed board.<<ETX>>\",\"PeriodicalId\":261113,\"journal\":{\"name\":\"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWRSP.1994.315899\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWRSP.1994.315899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A reconfigurable DSP board based on CORDIC elements
In this paper, a reconfigurable rapid prototyping system, oriented to DSP applications is proposed. Using the novel approach of combining the reconfigurability offered by an FPGA unit and the processing power of the CORDIC architecture, a fast, scalable and highly parallel structure has been developed. The results obtained by experimenting with the implementation of DCT algorithms are really promising, in terms of performance and versatility, which allows us to proceed for the development of a prototype that will be targeted to an image compression standard like H.261. Moreover, it is envisioned to build a parametrised library of hardware compilers that will map a wide range of DSP algorithms on the proposed board.<>
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