噪声-功率平衡两级运放CAD设计新方法

B. K. Mishra, Sandhya Save
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引用次数: 3

摘要

近年来,集成电路(如专用集成电路(ASIC)芯片)在速度、功率和复杂性方面都有了很大的进步。集成电路技术的进步导致了各种集成电路的诞生和扩散,包括但不限于特定应用的集成电路、微控制器、数字信号处理器、通用微处理器和网络处理器。ASIC(专用集成电路)技术已经从芯片组哲学发展到基于嵌入式核心的片上系统(SoC),即模拟和混合信号芯片(AMS)概念。许多应用,如通信设备(VoIP, MoIP,无线)需要芯片速度,这可能是单独的IC产品无法实现的。考虑到不同的设计约束,由于没有标准的模拟设计工具,90%的时间都花在模拟模块而不是数字模块的设计上,最大的问题是模拟电路的设计约束有时是隐含的,这使得将设计移植到新的环境中变得困难和容易失败。创建便携式模拟模块要求系统不仅要捕获电路的大小原理图,还要捕获电路试图实现的目标。本文将嵌入知识应用到基于纯仿真的方法中,对自动模拟集成电路进行设计、综合和优化,以缩短此类电路的开发时间。本文提出了一种实用的、独立于平台的、具有柔性噪声-功率平衡的(模拟电路)运算放大器合成的计算机辅助设计方法。为了在任意迭代的SA中评估电路规格的适应度,使用了NGSPICE仿真。仿真结果证实了该方法在确定模拟电路中器件尺寸方面的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance
In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips. Advances in integrated circuit technology have led to the birth and proliferation of a wide variety of integrated circuits, including but not limited to application specific integrated circuits, microcontrollers, digital signal processors, general purpose microprocessors, and network processors. ASIC (application specific integrated circuit) technology has evolved from a chip-set philosophy to an embedded core based system-on-a-chip (SoC) i.e. analog and mixed signal chip (AMS)concept. Many applications such as communication devices (VoIP, MoIP, wireless) require chip speeds that may be unattainable with separate IC products. Considering different design constraints, 90% of time is consumed while designing analog block rather than digital block due unavailability of standard analog design tool, also the largest problem is the design constraints of analog circuits are sometimes implicit, which makes porting the design to a new environment difficult and prone to failure. Creating portable analog modules requires the system to capture not only the sized schematic of the circuit but also the objectives that circuit is trying to achieved. This paper applies the embedding knowledge into pure simulation based methodology to perform automatic analog intergraded circuit design, synthesis and optimization in order to reduce development time of this kind of circuits. A practical platform independent computer aided design methodology for synthesis of (analog circuits) Operational Amplifier with flexible noise –power balance is presented in this paper. In order to evaluate the fitness of the circuit specifications in any iteration of SA, NGSPICE simulation is used. The simulation results confirm the efficiency of presented methodology in determining the device sizes in analog circuits.
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