用于0.13 /spl mu/m CMOS生成的坚固的嵌入式阶梯氧化物/Cu多层互连技术

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) Pub Date : 2002-06-11 DOI:10.1109/VLSIT.2002.1015377

N. Oda, S. Ito, T. Takewaki, H. Kunishima, N. Hironaga, I. Honma, H. Namba, S. Yokogawa, T. Goto, T. Usami, K. Ohto, A. Kubo, H. Aoki, M. Suzuki, Y. Yamamoto, S. Watanabe, T. Takeda, K. Yamada, M. Kosaka, T. Horiuchi

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引用次数: 7

摘要

为0.13 /spl mu/m CMOS代演示了一个稳健的嵌入式阶梯氧化物(k=2.9)/Cu多电平互连。稳定的阶梯氧化物IMD集成到Cu金属化中，最小布线间距为0.34 /spl mu/m，采用单damascene (S/D) Cu插头结构。与SiO/sub 2/ IMD相比，布线电容降低18%。宽金属上S/D铜塞结构的过孔应力迁移寿命远长于双damascene (D/D)结构。电迁移(EM)、铜互连TDDB、高压锅测试(PCT)等可靠性测试结果尚可接受。此外，在热设计和封装方面具有很高的灵活性。

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A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 /spl mu/m CMOS generation

A robust embedded ladder-oxide (k=2.9)/Cu multilevel interconnect is demonstrated for the 0.13 /spl mu/m CMOS generation. A stable ladder-oxide IMD is integrated into the Cu metallization with minimum wiring pitch of 0.34 /spl mu/m, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with SiO/sub 2/ IMD. The stress-migration lifetime of vias on wide metals for S/D Cu-plug structure is much longer than for dual damascene (D/D). The reliability test results such as those for electromigration (EM), Cu interconnect TDDB, and pressure cooker test (PCT) are quite acceptable. Moreover, high flexibility in thermal design and packaging is obtained.

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来源期刊

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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