Numerical Analysis of 4H-SiC MOSFET Design Including High-k Gate Dielectrics for Power electronic Applications

In this paper, we present a comprehensive investigation the impact of various high-k gate materials on both breakdown voltage and drain current of a vertical 4H-SiC-based power MOSFET, operating in the quasi-saturation regime. The device electrical behavior is numerically investigated using a TCAD-based computation provided by ATLAS 2D simulator. Moreover, the performance parameters, governing the power MOSFET breakdown characteristics are extracted in order to reveal the role of the high-k gate materials in improving the transistor electrical performance. The effect of the dielectric permittivity on the derived current capability in also analyzed. After, we conduct a sensitivity analysis of the breakdown voltage with several high-k materials (Al2O3, HfSiO4, HfO2, and TiO2) and different dielectric thicknesses. It is found that the proposed power MOSFET design exhibits improved electrical behavior not only enables enhancing the drain current but also allows achieving superior breakdown performance as compared to the conventional design, making it suitable for high-performance power electronic applications.