A Novel Circuit technique for Leakage Reduction in Ultra Deep Sub-Micron CMOS Technology

In ultra deep sub-micron technology due to extensive size reduction, leakage currents increases exponentially as a result of several short channel effects. In current scenario the leakage power consumption dominates the overall power consumption in high density chips. So it is a demand to control the static power consumption. In this work we have combined lector and drain gating techniques to get an architecture which uses the advantages of both the techniques. To further reduce the sub-threshold current, variable threshold voltage (VTCMOS) technique is also applied to the designed architecture. The performance of the designed logic gates are analysed in terms of static power consumption and average propagation delay. The performance of the proposed circuit has been compared with the reported techniques to validate our proposal. It is noticed that the proposed architectures reduces power consumption for the drain gating NOR gate by 48%, and for sleepy lector NOR gate by 20% considering 32nm technology.