不同铜/低钾互连孔内应力诱导空洞的数值表征

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) Pub Date : 2004-06-07 DOI:10.1109/IITC.2004.1345672

C. Yao, T.C. Huang, K. Chi, W. K. Wan, H.H. Lin, C. Hsia, M. Liang

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引用次数: 2

摘要

在这项工作中，提出了包括动态应力演化在内的建模方法，以表征各种Cu/低k互连内部的相对应力诱导空化(SIV)概率。选择了七种具有代表性的通用集成电路设计单元。仿真结果表明，该建模方法可以作为一种很好的方法来识别最麻烦的布局单元，并且结果与实验数据吻合得很好。从我们的研究中发现，两种布局风格在一起设计时是有害的:(1)有孔道的布局单元受到明显的上层金属边缘约束;(2)有孔道的布局单元靠近大空位源。

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Numerical characterization of the stress induced voiding inside via of various Cu/low k interconnects

Modelling methodologies including a dynamic stress evolution are proposed in this work to characterize the relative stress-induced voiding (SIV) probability inside via of various Cu/low k interconnects. Seven patterns being representative of versatile IC design units are selected. It is demonstrated that our modelling approach can serve as a good method identifying the most troublesome layout units to inside-via SIV, and the results aligned well with the experimental data. From our studies, two kinds of layout styles when designed together are found detrimental: (1) the layout units with via(s) subjected to significant upper-metal edge confinement and (2) the one with via close to big vacancy sources.

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Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

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