基于3倍盲adc的话单

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI:10.1109/ASSCC.2013.6691054

M. S. Jalali, Clifford Ting, Behrooz Abiri, A. Sheikholeslami, M. Kibune, H. Tamura

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引用次数: 4

摘要

本文采用3位ADC以3倍波特率对接收数据进行盲采样，恢复数据。通过从2x采样到3x采样，我们将所需的ADC分辨率从5位降低到3位，从而将总功耗降低了2倍。我们在富士通65nm CMOS上制造的测试芯片的测量显示，对于具有16”FR4通道的5Gbps PRBS31，高频抖动容差为0.19UIpp。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 3x blind ADC-based CDR

This paper uses a 3-bit ADC to blindly sample the received data at 3× the baud rate to recover the data. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu's 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16" FR4 channel.

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2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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